Patents by Inventor Teck-Chong Lee

Teck-Chong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178158
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Hsien KE, Teck-Chong LEE, Chih-Pin HUNG
  • Publication number: 20240170396
    Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Sheng-Wen YANG, Teck-Chong LEE, Yen-Liang HUANG
  • Patent number: 11894317
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Hsien Ke, Teck-Chong Lee, Chih-Pin Hung
  • Patent number: 11887928
    Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Sheng-Wen Yang, Teck-Chong Lee, Yen-Liang Huang
  • Patent number: 11855034
    Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 26, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung-Hung Lai, Chin-Li Kao, Chih-Yi Huang, Teck-Chong Lee
  • Publication number: 20230411349
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 21, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
  • Patent number: 11764311
    Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: September 19, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Pin Tsai, Tsung-Yueh Tsai, Teck-Chong Lee
  • Patent number: 11742324
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 29, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
  • Publication number: 20230261036
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Teck-Chong LEE
  • Publication number: 20230197600
    Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Sheng-Wen YANG, Teck-Chong LEE, Yen-Liang HUANG
  • Publication number: 20230178444
    Abstract: A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Teck-Chong LEE
  • Patent number: 11637172
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: April 25, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Teck-Chong Lee
  • Patent number: 11621220
    Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: April 4, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Chih-Pin Hung, Teck-Chong Lee, Chih-Yi Huang
  • Publication number: 20230092252
    Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 23, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Meng-Wei HSIEH, Teck-Chong LEE
  • Patent number: 11605877
    Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 14, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Chi Hsieh, Chen-Chao Wang, Teck-Chong Lee, Chien-Hua Chen
  • Patent number: 11545427
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Chien-Hua Chen, Teck-Chong Lee, Hung-Yi Lin, Pao-Nan Lee, Hsin Hsiang Wang, Min-Tzu Hsu, Po-Hao Chen
  • Publication number: 20220384381
    Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung-Hung LAI, Chin-Li KAO, Chih-Yi HUANG, Teck-Chong LEE
  • Patent number: 11515241
    Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 29, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Patent number: 11508655
    Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Meng-Wei Hsieh, Teck-Chong Lee
  • Patent number: 11495572
    Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee