Abstract: Various embodiments may provide an antenna system. The antenna system may include a printed circuit board including a circuit board ground element. The antenna system may also include a package over a surface of the printed circuit board. The antenna system may further include a radiating element parallel to the surface of the printed circuit board. The package may include a first encapsulation portion, and a radio frequency integrated circuit chip embedded in the first encapsulation portion, the radio frequency integrated circuit chip parallel to the surface of the printed circuit board. The package may additionally include a package ground element over the first encapsulation portion and in electrical connection with the circuit board ground element, the package ground element parallel to the surface of the printed circuit board, and a second encapsulation portion between the package ground element and the radiating element.

Abstract: Various embodiments may provide a semiconductor package. The semiconductor package may include a substrate including a via hole. The semiconductor package may also include a chip attached to the substrate. The semiconductor package may further include a prefabricated ferromagnetic pin having a first portion held by the via hole, a second portion extending from a first end of the first portion, and a third portion extending from a second end of the first portion opposite the first end. The semiconductor package may also include a first magnetic shield structure attached to or extended from the second portion of the prefabricated ferromagnetic pin. The semiconductor package may further include a second magnetic shield structure attached to or extended from the third portion of the prefabricated ferromagnetic pin, such that at least a portion of the chip is between the first magnetic shield structure and the second magnetic shield structure.

Abstract: Various embodiments may provide an optical assembly. The optical assembly may include a substrate with a first and a second grooves, and a photonic integrated circuit chip with a coupling waveguide, a first and a second grooves. The optical assembly may further include a first and a second cylindrical rods held by the respective grooves of the substrate and the photonic integrated circuit chip. A portion of the first rod and a portion of the second rod define a vertical offset between the photonic integrated circuit chip and the substrate to align the coupling waveguide with an optical fiber.

Abstract: Various embodiments may relate to a method of forming a photonic integrated circuit package (PIC). The method may include forming a redistribution layer (RDL) over a carrier. The method may also include forming a through hole or cavity on the redistribution layer. The method may additionally include providing a stop-ring structure, the stop-ring structure including a ring of suitable material, the stop-ring structure defining a hollow space, over the redistribution layer so that the hollow space is over the through hole or cavity. The method may further include arranging a photonic integrated circuit (PIC) die over the redistribution layer so that the photonic integrated circuit (PIC) die is on the stop-ring structure. The method may also include forming a molded package by forming a mold structure to at least partially cover the photonic integrated circuit (PIC) die to form the photonic integrated circuit package.

Abstract: Various embodiments may provide an optical assembly. The optical assembly may include a substrate with a first and a second grooves, and a photonic integrated circuit chip with a coupling waveguide, a first and a second grooves. The optical assembly may further include a first and a second cylindrical rods held by the respective grooves of the substrate and the photonic integrated circuit chip. A portion of the first rod and a portion of the second rod define a vertical offset between the photonic integrated circuit chip and the substrate to align the coupling waveguide with an optical fiber.

Abstract: Various embodiments may provide a semiconductor package. The semiconductor package may include a substrate including a via hole. The semiconductor package may also include a chip attached to the substrate. The semiconductor package may further include a prefabricated ferromagnetic pin having a first portion held by the via hole, a second portion extending from a first end of the first portion, and a third portion extending from a second end of the first portion opposite the first end. The semiconductor package may also include a first magnetic shield structure attached to or extended from the second portion of the prefabricated ferromagnetic pin. The semiconductor package may further include a second magnetic shield structure attached to or extended from the third portion of the prefabricated ferromagnetic pin, such that at least a portion of the chip is between the first magnetic shield structure and the second magnetic shield structure.

Abstract: Various embodiments may relate to a method of forming a photonic integrated circuit package (PIC). The method may include forming a redistribution layer (RDL) over a carrier. The method may also include forming a through hole or cavity on the redistribution layer. The method may additionally include providing a stop-ring structure, the stop-ring structure including a ring of suitable material, the stop-ring structure defining a hollow space, over the redistribution layer so that the hollow space is over the through hole or cavity. The method may further include arranging a photonic integrated circuit (PIC) die over the redistribution layer so that the photonic integrated circuit (PIC) die is on the stop-ring structure. The method may also include forming a molded package by forming a mold structure to at least partially cover the photonic integrated circuit (PIC) die to form the photonic integrated circuit package.

Abstract: Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

Abstract: Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

Abstract: A wafer level package is provided. The wafer level package includes at least one chip with at least one electronic component, and at least one connecting chip with at least one through-silicon via, wherein the at least one through-silicon via is electrically coupled to the at least one chip. Further embodiments relate to a method of forming the wafer level package.