Patents by Inventor Teck Jung Tang
Teck Jung Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9947645Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.Type: GrantFiled: June 26, 2015Date of Patent: April 17, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD., ENESAS ELECTRONICS CORPORATIONInventors: Soon Yoeng Tan, Teck Jung Tang, Ian D. Melville, Yelei Vianna Yao, Yasushi Yamagata
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Patent number: 9576894Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.Type: GrantFiled: June 3, 2015Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Xusheng Wu, Akshey Sehgal, Teck Jung Tang
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Publication number: 20160358851Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Xusheng Wu, Akshey Sehgal, Teck Jung Tang
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Patent number: 9362162Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).Type: GrantFiled: August 14, 2014Date of Patent: June 7, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Teck Jung Tang, Mark Alexander Zaleski
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Publication number: 20160049327Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).Type: ApplicationFiled: August 14, 2014Publication date: February 18, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Sunil Kumar SINGH, Ravi Prakash SRIVASTAVA, Teck Jung TANG, Mark Alexander ZALESKI
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Publication number: 20150348907Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Inventors: Sunil Kumar SINGH, Matthew HERRICK, Teck Jung TANG, Dewei XU
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Publication number: 20150294964Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.Type: ApplicationFiled: June 26, 2015Publication date: October 15, 2015Inventors: Soon Yoeng TAN, Teck Jung TANG, Ian D. MELVILLE, Yelei Vianna YAO, Yasushi YAMAGATA
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Patent number: 9142451Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.Type: GrantFiled: September 16, 2013Date of Patent: September 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Sunil Kumar Singh, Matthew Herrick, Teck Jung Tang, Dewei Xu
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Patent number: 9105507Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.Type: GrantFiled: January 13, 2015Date of Patent: August 11, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
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Patent number: 9069923Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.Type: GrantFiled: June 16, 2011Date of Patent: June 30, 2015Assignees: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Soon Yoeng Tan, Teck Jung Tang, Ian D. Melville, Yelei Vianna Yao, Yasushi Yamagata
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Publication number: 20150123214Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.Type: ApplicationFiled: January 13, 2015Publication date: May 7, 2015Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
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Publication number: 20150076705Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.Type: ApplicationFiled: September 16, 2013Publication date: March 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Sunil Kumar SINGH, Matthew HERRICK, Teck Jung TANG, Dewei XU
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Patent number: 8969932Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.Type: GrantFiled: December 12, 2012Date of Patent: March 3, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
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Publication number: 20140159126Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
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Patent number: 8637993Abstract: A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.Type: GrantFiled: April 23, 2012Date of Patent: January 28, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Chun Yu Wong, Ramakanth Alapati, Teck Jung Tang
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Publication number: 20130277854Abstract: A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.Type: ApplicationFiled: April 23, 2012Publication date: October 24, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Chun Yu Wong, Ramakanth Alapati, Teck Jung Tang
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Publication number: 20120319246Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., RENESAS ELECTRONICS CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Soon Yoeng TAN, Teck Jung TANG, Ian D. MELVILLE, Yelei Vianna YAO, Yasushi YAMAGATA
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Patent number: 8283193Abstract: A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region.Type: GrantFiled: August 14, 2009Date of Patent: October 9, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Soon Yoeng Tan, Teck Jung Tang
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Patent number: 7906426Abstract: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.Type: GrantFiled: April 23, 2007Date of Patent: March 15, 2011Assignees: Globalfoundries Singapore Pte. Ltd., International Business Machines Corporation, Infineon Technologies AGInventors: Wuping Liu, Johnny Widodo, Teck Jung Tang, Jing Hui Li, Han Wah Ng, Larry A. Clevenger, Hermann Wendt
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Publication number: 20110037140Abstract: A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region.Type: ApplicationFiled: August 14, 2009Publication date: February 17, 2011Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Soon Yoeng Tan, Teck Jung Tang