Abstract: A method for manufacturing a surface mount solder pad that is adapted to function as a heat sink for an electronic component soldered to the pad. The method comprises a step of providing a printed wiring board having a conductive layer disposed thereon. The method further comprises a step of selecting a size and arrangement of regions of a solder pad so as to sink sufficient heat. The method also comprises removing non-selected regions of the conductive layer to produce solder pads on the surface of the printed wiring board enhanced with features that promote heat transfer to sink enough heat generated by one of the surface mount components to provide for its proper operation.

Abstract: A battery management system and method for an electronic device that may be powered by an AC source (using an AC adapter), or by a battery. The battery management system includes firmware configured to determine whether a battery coupled to the electronic device is rechargeable. The firmware is also coupled to and configured to control a charge switch. When the battery and an AC source are both coupled to the device, activating the charge switch causes a charging current to be applied from the AC source to the battery. The charge switch and firmware are configured to cause the charging current to not be applied to the battery if it is determined that the battery is not rechargeable.

Abstract: A battery management system and method for an electronic device that may be powered by an AC source (using an AC adapter), or by a battery. The battery management system includes firmware configured to determine whether a battery coupled to the electronic device is rechargeable. The firmware is also coupled to and configured to control a charge switch. When the battery and an AC source are both coupled to the device, activating the charge switch causes a charging current to be applied from the AC source to the battery. The charge switch and firmware are configured to cause the charging current to not be applied to the battery if it is determined that the battery is not rechargeable.

Abstract: A surface mount solder pad that is adapted to function as a heat sink for an electronic component soldered to the pad. Included is a printed wiring board having solder pads disposed on its surface that are adapted for soldering to leads of surface mount components. The solder pads are electrically interconnected by conductive traces also disposed on the surface. At least one of the solder pads has an enhanced surface area that is selected larger than necessary for the soldering, and that is selected sufficiently large so as to sink enough heat generated by one of the surface mount components to provide for its proper operation.

Abstract: A method for manufacturing a surface mount solder pad that is adapted to function as a heat sink for an electronic component soldered to the pad, wherein the surface of the solder pad is larger than necessary for soldering and the surface is additionally enhanced with features that promote heat transfer. Included is a printed wiring board having solder pads disposed on its surface that are adapted for soldering to leads of surface mount components. The solder pads are electrically interconnected by conductive traces also disposed on the surface. At least one of the solder pads has an enhanced surface area that is selected larger than necessary for the soldering, and that is selected sufficiently large so as to sink enough heat generated by one of the surface mount components to provide for its proper operation.

Abstract: A bidirectional asynchronous open collector buffer. The buffer employs set delays and control logic to prevent latch up of the buffer when the low signal is applied to one of the ports of the buffer. Additionally, the buffer employs reset delays in conjunction with the control logic for suppressing oscillation of the buffer when one of the ports of the buffer is released from the applied low signal.

Abstract: A switching multiplexor arrangement of relays having configuration flexibility and operative for balancing thermal offset of the relays Accumulated thermal offset of the relays along the various propagation paths through the multiplexor is balanced, by maintaining equal numbers of configured relays, along the various propagation paths, so that there are substantially equal amounts of accumulated thermal offset for the various propagation paths.

Abstract: A cache output selector for a multi-way set-associative cache memory which provides for simultaneous access of multiple-word data is presented. The cache memory comprises a plurality of data arrays wherein no two consecutive multiple-word reside in the same data. The cache output selector of the present invention includes, for each data array of the plurality of data arrays, a qualifying multiplexor which receives the respective tag match signals from each of the tag matching circuits as data input and a set selector signal, as selector input, and at least one qualifying signal as qualifying input. The set selector signal indicates which data array a first set of the multi-way set-associative memory resides in during a current read/write cycle. The qualifying multiplexor combines a clock qualifying functionality and a multiplexor functionality to produce a data array output enable signal in only two levels of logic.

Abstract: Disclosed herein are methods and apparatus relating to speed optimal bit ordering in a cache memory. All of the data arrays capable of driving a single output bit are grouped with combinational I/O logic for driving same. The data arrays and combinational I/O logic corresponding to a single output bit can be thought of as a bit slice of a cache. Bit slices are preferably arranged so that predecode bit slices are nearest to the I/O end of the cache. A number of predecode bit slices corresponding to a single instruction or data word are preferably followed by the instruction's predecode data bit slices. Non-predecode data bit slices are arranged so that big/little endien data bit pairs are adjacent to one another, or as close to each other as possible given other bit slice ordering restraints. The arrangement of bit slices in big/little endien pairs yields I/O buses of minimum length. Components of combinational I/O logic are arranged in staggered form, perpendicularly to the I/O datapath of a cache.