Patents by Inventor Ted Bruce

Ted Bruce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip stack with differing chip package types
    Patent number: 6908792
    Abstract: A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: June 21, 2005
    Assignee: Staktek Group L.P.
    Inventors: Ted Bruce, John A. Forthun
  • Chip stack with differing chip package types
    Patent number: 6627984
    Abstract: A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: September 30, 2003
    Assignee: Dense-Pac Microsystems, Inc.
    Inventors: Ted Bruce, John A. Forthun
  • Chip stack with differing chip package types
    Publication number: 20030025211
    Abstract: A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.
    Type: Application
    Filed: October 3, 2002
    Publication date: February 6, 2003
    Inventors: Ted Bruce, John A. Forthun
  • Chip stack with differing chip package types
    Publication number: 20030020153
    Abstract: A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.
    Type: Application
    Filed: July 24, 2001
    Publication date: January 30, 2003
    Inventors: Ted Bruce, John A. Forthun