Abstract: A circuit/packaging arrangement for terminating and decoupling emitter coupled logic comprises a plurality of terminating impedance components (resistors) and decoupling capacitor one end of each of which is connected via a common conductor to one pair of a multi-pin single-in-line package (SIP). The other ends of the terminating impedance and the capacitor are connected to respective terminal pins adjacent to the one pin of the SIP. The decoupling capacitor that is coupled with the terminating resistors is located, both physically and electrically, at the middle of the distribution or terminating resistors contained within the SIP, such that the resistors are distributed effectively/symmetrically on either side of the capacitor. This location of the capacitor effectively in the middle of the terminating network minimizes line inductance of the common (-2v) conductor to which one end of each of the resistors is connected.