Abstract: A method for manufacturing a silicon bipolar power high frequency transistor device is disclosed. A transistor device according to the present method is also disclosed. The transistor device assures conditions for maintaining a proper BVCER to avoid collector emitter breakdown during operation. According to the method an integrated resistor (20) is arranged along at least one side of a silicon bipolar transistor (1) on a semiconductor die which constitutes a substrate for the silicon bipolar transistor. The integrated resistor is connected between the base and emitter terminals of the silicon bipolar transistor (1). The added integrated resistor (20) is a diffused p+ resistor on said semiconductor die or a polysilicon or NiCr resistor placed on top of the isolation layers. In an interdigitated transistor structure provided with integrated emitter ballast resistors the added resistor or resistors (20) will be manufactured in a step simultaneously as producing the ballast resistors.

Abstract: A method for manufacturing a silicon bipolar power high frequency transistor device is disclosed. A transistor device according to the present method is also disclosed. The transistor device assures conditions for maintaining a proper BVCER to avoid collector emitter breakdown during operation. According to the method an integrated resistor is arranged along at least one side of a silicon bipolar transistor on a semiconductor die which constitutes a substrate for the silicon bipolar transistor. The integrated resistor is connected between the base and emitter terminals of the silicon bipolar transistor. The added integrated resistor is a diffused p+ resistor on said. semiconductor die or a polysilicon or NiCr resistor placed on top of the isolation layers. In an interdigitated transistor structure provided with integrated emitter ballast resistors the added resistor or resistors will be manufactured in a step simultaneously as producing the ballast resistors.

Abstract: In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics, comprising the steps of:

Abstract: A method for manufacturing a low voltage high frequency silicon power transistor applying epitaxial mesa structure using a minimized number of masks has a highly doped silicon n++ substrate forming the emitter. Also a low voltage high frequency silicon transistor chip presenting an epitaxial mesa technology silicon power device is presented. The silicon transistor layout presents a collector-up device with a number of single mesa collector structures. The transistor operates with its substrate as a down facing emitter, and base and collector areas together with bonding pads facing up, whereby the parasitic base-to-collector capacitance is almost entirely eliminated with the emitter as substrate. The reduced number of necessary fabrication process steps of this new structure is outlined.

Abstract: The present invention relates to a method for semiconductor manufacturing of one semiconductor circuit, having a multiple of transistors NMOS1, NMOS2, NPN1, NPN2 of one type. The method comprises the steps of arranging a first region 4, 16 on a semiconductor substrate 1, and implementing two transistors of said type, having different sets of characteristics, in said first region 4, 16. The step of implementing said active devices comprises a step of creating a first 6′, 10′ and a second 6″, 10″ subregion within said first region 4, 16, and said step further comprising a step of introducing dopants having different sets of dose parameters, into a first and a second area, respectively, of said first region, said dopants being of a similar type, and a step of annealing said substrate 1 to create said first 6′, 10′ and second 6″, 10″ subregion, respectively, whereby two subregions, having different doping profiles, can be manufactured on a single integrated circuit.

Abstract: The present disclosure describes a method to reduce the base-collector capacitance swing and increase the collector-to-base breakdown voltage in a bipolar high-frequency transistor. First a highly doped silicon substrate (1) of a first doping is selected for forming a transistor emitter region. Then layers (5, and 6, 7) are deposited with a second and a first doping for forming a base/collector structure. Subsequently a collector mesa structure is formed by removing silicon on base contact areas using a photoresist mask on top of a layer of for instance an oxide (9) so that the additional layers also serve as a mask for the silicon etch. An etching method is selected to facilitate the form of the collector to be made narrow closer to a collector contact surface, thereby creating a bipolar collector-up high frequency transistor with a shaped collector. This improves both the capacitance swing and the breakdown voltage.

Abstract: The present invention relates to a method for semiconductor manufacturing of one semiconductor circuit, having a multiple of transistors NMOS1, NMOS2, NPN1, NPN2 of one type. The method comprises the steps of arranging a first region 4, 16 on a semiconductor substrate 1, and implementing two transistors of said type, having different sets of characteristics, in said first region 4, 16. The step of implementing said active devices comprises a step of creating a first 6′, 10′ and a second 6″, 10″ subregion within said first region 4, 16, and said step further comprising a step of introducing dopants having different sets of dose parameters, into a first and a second area, respectively, of said first region, said dopants being of a similar type, and a step of annealing said substrate 1 to create said first 6′, 10′ and second 6″, 10″ subregion, respectively, whereby two subregions, having different doping profiles, can be manufactured on a single integrated circuit.

Abstract: The present invention relates to a vertical bipolar power transistor primarily intended for radio frequency applications and to a method for manufacturing, the bipolar power transistor. The power transistor comprises a substrates, a collector layer of a first conductivity type on the substrate, a base of a second conductivity type electrically connected to the collector layer, an emitter of the first conductivity type electrically connected to the base, the base and the emitter each being electrically connected to a metallic interconnecting layer, the interconnecting layers being at least in parts separated from the collector layer by an insulation oxide. According to the invention the power transistor substantially comprises a field shield electrically connected to the emitter, and located between the metallic interconnecting layer of the base and the insulation oxide.

Abstract: A bipolar power transistor intended for radio frequency applications, especially for use in an amplifier stage in a radio base station, and a method for manufacturing the bipolar power transistor are provided. The power transistor includes a substrate (13), an epitaxial collector layer (15) on the substrate (13), a base (19) and an emitter (21) formed in the collector layer (15). The degree of doping Nc(x) of the collector layer varies from its upper surface (24) and downwards to at least half the depth of the collector layer, essentially according to a polynom of at least the second degree, a0+a1x+a2x2+ . . . , where a0 is the degree of doping at the upper surface (24), x is the vertical distance from the same surface (24) and a1, a2, . . . are constants. The transistor can further include an at least approximately 2&mgr; thick insulation oxide (17) between the epitaxial collector layer (15) and higher situated metallic connections layers (31, 33).

Abstract: An impedance device has a first conductor and a second conductor, the first and second conductors being positioned in relation to each other so as to provide magnetic coupling between them. The impedance of the impedance device is controlled by receiving, in the first conductor, a first electric signal having a first amplitude and a first phase angle, generating a second electric signal having a second amplitude and a second phase angle, delivering the second electric signal to the second conductor, and controlling the second phase angle.

Abstract: The present invention relates to a vertical bipolar power transistor primarily intended for radio frequency applications and to a method for manufacturing the bipolar power transistor. The power transistor comprises a substrate (13), a collector layer (15) of a first conductivity type on the substrate, a base (19) of a second conductivity type electrically connected to the collector layer, an emitter (21) of the first conductivity type electrically connected to the base, the base and the emitter each being electrically connected to a metallic interconnecting layer (31,33), the interconnecting layers (31,33) being at least in parts separated from the collector layer (15) by an insulation oxide (17). According to the invention the power transistor substantially comprises a field shield (25) electrically connected to the emitter, and located between the metallic interconnecting layer of the base and the insulation oxide.

Abstract: The present invention, generally speaking, provides an apparatus and method whereby the current flow through an RF power transistor may be monitored without the use of any external parts. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, a pair of interdigitated electrodes formed on the silicon die, each having a multiplicity of parallel electrode fingers and at least one bond pad. Regions of a first type of diffusion are formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion are formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes. One electrode has multiple electrode fingers and multiple resistors formed on the silicon die, at least one resistor connected in series with each one of the electrode fingers.

Abstract: An RF power transistor having improved thermal balance characteristics includes a first emitter electrode and a base electrode formed on a silicon die, each having a multiplicity of parallel electrode fingers. A second emitter electrode is formed over the base electrode, and is electrically connected to the first emitter electrode. Ballast resistors are formed in a substantially evenly spaced manner on each side the silicon die, in series with at least some of the electrode fingers of the first emitter electrode and in series of at least some of the electrode fingers of the second emitter electrode.

Abstract: An apparatus and method are provided for bypassing the emitter ballast resistors of a power transistor, thereby increasing transistor gain. In a power transistor of the interdigitated type, bypassing the emitter ballast resistors requires bypassing each individual ballast resistor with a capacitor in parallel. Bypassing is therefore done on the silicon chip. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, an emitter ballast resistor formed on the silicon die, and a bypass capacitor formed on the silicon die and connected in parallel with the emitter ballast resistor. The resistor may be a diffused resistor, and the capacitor may be a metal-on-polysilicon capacitor.

Abstract: A method for creating a MOS-type capacitor structure in function blocks or integrated circuits. Each block or cell is provided with capacitors for decoupling purposes under the board metal supply lines without requiring any extra silicon surface. The buried capacitors can be designed under any board conductor path or on a chip made of a semiconductor material.

Abstract: A method for creating a MOS-type capacitor structure in function blocks or integrated circuits. Each block or cell is provided with capacitors for decoupling purposes under the broad metal supply lines without requiring any extra silicon surface. The buried capacitors can be designed under any broad conductor path or on a chip made of a semiconductor material.

Abstract: A layout is provided for RF power transistors that reduces common lead inductance and its associated performance penalties. An RF transistor cell is rotated 90.degree. with respect to a conventional RF transistor cell so as to located bond pads nearer the edge of a silicon die, reducing bond wire length and common lead inductance and thereby improving performance at high frequencies. The placement of bond pad and distribution of different parts of the transistor layout further reduces common lead inductance.