Abstract: Methods and systems for verifying that devices in a network are properly connected physically are described. A listing is received from a device in the network. The listing identifies other devices coupled to the device and also identifies which communication port of the device each of the other devices is coupled to. The listing is compared against reference information representing the design of the network. Discrepancies between the listing and the reference information are identified.

Abstract: Systems, methods, and device are provided for device status identification. One method embodiment includes transmitting an SNMP message to a device. The method includes opening a socket connection on the device in response to an SNMP error message returned from the device. And, the method includes initiating a time-out function upon opening the socket connection.

Abstract: Methods and systems for verifying that devices in a network are properly connected physically are described. A listing is received from a device in the network. The listing identifies other devices coupled to the device and also identifies which communication port of the device each of the other devices is coupled to. The listing is compared against reference information representing the design of the network. Discrepancies between the listing and the reference information are identified.

Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: A circuit is disclosed herein which generates the sum of two numbers (A and B) and the sum plus 1 in parallel so as not to take any additional time to generate the sum plus 1 value. The circuit comprises a carry look-ahead (CLA) tree portion and a summer portion. The CLA tree portion generates carry bits, as well as the logical relationship A.sub.i XOR B.sub.i, for application to a summer for bit position i. The carry bits contain information for either inverting or not inverting the A.sub.i XOR B.sub.i bit for both the sum and the sum plus 1 output of the summer. The sum bit and sum plus 1 bit are generated at approximately the same time.

Abstract: A floating point unit (FPU) is described which processes normalized binary numbers. All multiply, add, and subtract calculations are performed using the format (A*B)+C or (A*B)-C. The operation A*B is performed in parallel with the alignment of C to the product of A*B. An output of the multiplier and the aligned operand C are applied to a carry save adder, whose output is then applied to a carry propagate adder to generate the result A*B.+-.C. The output of the carry save adder is also applied to a combined leading one anticipator (LOA) and leading zero anticipator (LZA). The output of the carry propogate adder is provided to a post normalizer. The output of the combined LOA/LZA is applied to the input of a multiplexer, with the control input of the multiplexer being connected to the most significant bit of the adder output, where this most significant bit indicates whether the result is positive or negative.

Abstract: A leading zero counter or anticipator is described herein which uses a 36-bit-wide bus. The bus can handle four 8 or 9-bit words, two 16-bit words, or one 32-bit word. The leading zero counter has an encoder section, a logic section, and a multiplexer section. Four encoders each receive a separate group of bits. A logic circuit receives the encoded signals and generates the leading zero count(s) for the binary number(s) on the 36-bit bus. The logic circuit is able to simultaneously generate four leading zero counts if the word size is 8 or 9 bits, two leading zero counts if the word size is 16 bits, or one leading zero count if the word size is 32 bits. A multiplexer connected between the logic circuit and a 36-bit output bus receives a control signal that indicates the word size of either 8, 9, 16, or 32 bits and applies the appropriate leading zero counts from the logic circuit to the appropriate bit positions on the output bus.