Patents by Inventor Ted Rossin

Ted Rossin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for determining victim row addresses in a volatile memory
    Patent number: 9824754
    Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw, John H. Crawford
  • Techniques for Determining Victim Row Addresses in a Volatile Memory
    Publication number: 20160224262
    Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
    Type: Application
    Filed: January 19, 2016
    Publication date: August 4, 2016
    Applicant: INTEL CORPORATION
    Inventors: SREENIVAS MANDAVA, BRIAN S. MORRIS, SUNEETA SAH, ROY M. STEVENS, TED ROSSIN, MATHEW W. STEFANIW, JOHN H. CRAWFORD
  • Techniques for determining victim row addresses in a volatile memory
    Patent number: 9269436
    Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 23, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw, John H. Crawford
  • Techniques for Determining Victim Row Addresses in a Volatile Memory
    Publication number: 20140281207
    Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
    Type: Application
    Filed: December 18, 2013
    Publication date: September 18, 2014
    Inventors: Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw, John H. Crawford