Abstract: A method of producing a plate-like construction having a double-wall structure and its use. According to the present invention, several elongated profiles which have essentially straight central axes are arranged against each other in such a way that adjacent hollow profiles abut each other and together form, in general terms, a flat stack having two opposite sides. The hollow profiles are welded together in order to join them with welded seams, in which case the welding is essentially carried out simultaneously from both sides of the stack. Besides good flexural strength and the opportunity to recycle, thermoplastic plates which are produced by means of the present method exhibit resistance to corrosion, decay and mould.

Abstract: A method of producing a plate-like construction having a double-wall structure and its use. According to the present invention, several elongated profiles which have essentially straight central axes are arranged against each other in such a way that adjacent hollow profiles abut each other and together form, in general terms, a flat stack having two opposite sides. The hollow profiles are welded together in order to join them with welded seams, in which case the welding is essentially carried out simultaneously from both sides of the stack. Besides good flexural strength and the opportunity to recycle, thermoplastic plates which are produced by means of the present method exhibit resistance to corrosion, decay and mould.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C4F8 and/or C4F6, an oxygen source, and a carrier gas in combination with tetrafluoroethane (C2F4) or a halofluorocarbon analogue of C2F4.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C4F8 and/or C4F6, an oxygen source, and a carrier gas in combination with tetrafluoroethane (C2F4) or a halofluorocarbon analogue of C2F4.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: An adhesive shelf talker is provided with upper and lower end portions that are selectively separable from one another. The upper end portion provides non-promotional product information, while the lower end portion provides the promotional information for the product. A two-part release liner is provided so that the upper end portion may adhere to a shelf edge while leaving the lower end portion of the shelf talker, which hangs below the shelf, unexposed.

Abstract: The invention provides a unique method and apparatus for detecting defects in an electronic device. In one preferred embodiment, the electronic device is a semiconductor integrated circuit (IC), particularly one of a plurality of IC dies fabricated on a wafer of silicon or other semiconductor material. The defect detection operation is effectuated by a unique combination of critical dimension measurement and pattern defect inspection techniques. During the initial scan of the surface of the wafer, in an attempt to locate the appropriate area for a critical dimension (CD) feature or element that is to be measured, a “best fit” comparison is made between a reference image and scanned images. The critical dimension measurements are conducted on a “best fit” image. In addition, a “worst fit” comparison is made between the reference and scanned images. A “worst fit” determination represents pattern distortions or defects in the ICs under evaluation.

Abstract: A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.

Abstract: The invention provides a unique method and apparatus for detecting defects in an electronic device. In one preferred embodiment, the electronic device is a semiconductor integrated circuit (IC), particularly one of a plurality of IC dies fabricated on a wafer of silicon or other semiconductor material. The defect detection operation is effectuated by a unique combination of critical dimension measurement and pattern defect inspection techniques. During the initial scan of the surface of the wafer, in an attempt to locate the appropriate area for a critical dimension (CD) feature or element that is to be measured, a “best fit” comparison is made between a reference image and scanned images. The critical dimension measurements are conducted on a “best fit” image. In addition, a “worst fit” comparison is made between the reference and scanned images. A “worst fit” determination represents pattern distortions or defects in the ICs under evaluation.

Abstract: A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.

Abstract: A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.