Abstract: Apparatus and methods for mitigation and control of inflammatory responses during usage of an implantable sensor device. In one exemplary embodiment, the implantable sensor device includes a drug-eluting component configured to release a varying amount of anti-inflammatory substance(s) (such as corticosteroid) over the lifetime of the implant, such as according to a desired elution profile. In one variant, this component is also an analyte-permeable membrane used as part of a detector of the implant. Inhibition of inflammation in the tissue improves availability of analytes (such as oxygen and glucose) to the sensor in addition to reducing fibrous encapsulation. Various modifications to the elution rate, and configuration of the implant, allow optimized control over undesirable effects such as foreign body reactions (FBR) or other inflammatory responses which may reduce usable implant lifetime.

Abstract: A system and a method of using the system for reproducibly cutting a cove using a table saw are presented. The system comprises a first fence assembly and a fixturing means, where the fence assembly is rotatably affixed to the fixturing means, wherein the fixturing means can be releasably secured to the table of the table saw. The method comprises providing a blank molding, a table saw having a table and saw blade, and the cove system and releasably affixing the cove system to the table. The method further comprises setting a fence angle using the first fence assembly and setting a fence depth by adjusting the position of the fixturing means with respect to the table. The method finally comprises feeding the blank molding over the saw blade thereby cutting a cove in the blank molding.

Abstract: A system and a method of using the system for reproducibly cutting a cove using a table saw are presented. The system comprises a first fence assembly and a fixturing means, where the fence assembly is rotatably affixed to the fixturing means, wherein the fixturing means can be releasably secured to the table of the table saw. The method comprises providing a blank molding, a table saw having a table and saw blade, and the cove system and releasably affixing the cove system to the table. The method further comprises setting a fence angle using the first fence assembly and setting a fence depth by adjusting the position of the fixturing means with respect to the table. The method finally comprises feeding the blank molding over the saw blade thereby cutting a cove in the blank molding.

Abstract: An efficient software download to a configurable communication device is disclosed herein. The method of efficiently downloading software begins with a step of receiving a request to configure a communication device to run a communication application. The communication device being configured has a plurality of function blocks with a fixed portion of hardware and a flexible portion of hardware, wherein the same plurality of function blocks is capable of operating a plurality of communication applications. In a next step, the capability of the fixed portion and the flexible portion of hardware of the communication device is evaluated for a capability of implementing the communication application. Next, configuration information only for the flexible portion of hardware of the communication device is transmitted to the communication device to enable it to operate the communication application.

Abstract: A pullup circuit having a limited voltage swing and fast pullup and pulldown times comprises a pullup structure, a pulldown structure and an internal node. The pullup circuit operates to limit the current of the pullup structure before the N-tree discharges the internal node, thereby reducing the pullup effect of the pullup structure to reduce fall time and power consumption. Then the pullup circuit maximizes the current of the pullup structure after the N-tree has pulled down the internal node to increase the pullup effect of the pullup structure to reduce rise time. As a result, the voltage of the internal node both charges more quickly when the N-tree becomes inactive and discharges more quickly when the N-tree becomes active.

Abstract: A multiplier tree sums the partial products of a multiplication operation, employing a regular hierarchical arrangement of bit adders that accept nine initial inputs and a carry input and produce three outputs and a carry output. The regularity of the structure of the bit adder allows it be used to form an array of bit adders to sum twenty-seven input bits and ten carry input bits to produce three output bits and ten carry outputs bits. These bit adders form the basis of the multiplier tree. The multiplier tree using this structure can sum the partial products from a 52 to 54 bit multiply operation in no more adder delays than a Wallace tree, but with a more regular structure. A method for reducing nine input signals to three output signals segregates the input signals into sets of signals and combines them into reduced sets of logically equivalent signals.

Abstract: A structure of logic gates, partial product circuits, and a multiplier tree is described for multiplying of two operands which may contain denormalized numbers in the same amount of time as needed to multiply normalized numbers. The generation of the most significant bits ("hidden bits") of the significands of the operands from the operand exponents, and the production of the partial products that are dependent on these hidden bits, is accomplished in parallel with the generation of the partial products of the expressed bits of the significands of the operands and the first level of the multiplier tree. The fraction field partial products are input into the top level of a multiplier tree comprised of various order adders and wires. The hidden bit partial products are then input into the body of the multiplier tree instead of the top level. Additional adders are allocated to accommodate these additional inputs, but without lengthening the longest serial path from the top to the bottom of the multiplier tree.

Abstract: Apparatus and methods for early quotient completion in arithmetic division include a quotient digit generator, one or more asynchronous shift registers and a remainder comparison block. As quotient digits are generated, each digit is transferred to a different asynchronous shift register in turn. Digits are immediately propagated down each shift register to the next most significant digit position. During propagation digits are also repeated at all lesser significant digit positions. At the end of a digit generation cycle, when all asynchronous shift registers have received one new digit, the remainder comparison block determines if the current remainder is the same as the last period's remainder. If not, the remainder comparison block sends a reset signal to all the shift registers, sending reset spacers along each register that reset all duplicate versions of the last digits sent. The registers are then ready to receive next period's series of quotient digits.