Patents by Inventor Teddy Joaquin CARREON

Teddy Joaquin CARREON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384505
    Abstract: A semiconductor device has a substrate. A semiconductor die including a photosensitive circuit is disposed over the substrate. A shield is disposed over the substrate and semiconductor die with a first opening of the shield disposed over the photosensitive circuit. An outer section of the shield is attached to the substrate and includes a second opening. An encapsulant is deposited over the substrate and semiconductor die. The encapsulant extends into the first opening and a first area between the shield and substrate while a second area over the photosensitive circuit remains devoid of the encapsulant.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 1, 2022
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: Emmanuel Espiritu, Il Kwon Shim, Jeffrey Punzalan, Teddy Joaquin Carreon
  • Publication number: 20210366963
    Abstract: A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Il Kwon SHIM, Jeffrey PUNZALAN, Emmanuel ESPIRITU, Allan ILAGAN, Teddy Joaquin CARREON
  • Patent number: 11177301
    Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: November 16, 2021
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Hua Hong Tan, Chee Kay Chow, Thian Hwee Tan, Wedanni Linsangan Micla, Enrique Jr Sarile, Mario Arwin Fabian, Dennis Tresnado, Antonino Ii Milanes, Ming Koon Ang, Kian Soo Lim, Mauro Jr. Dionisio, Teddy Joaquin Carreon
  • Publication number: 20200161351
    Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 21, 2020
    Inventors: Hua Hong TAN, Chee Kay CHOW, Thian Hwee TAN, Wedanni Linsangan MICLA, Enrique Jr SARILE, Mario Arwin FABIAN, Dennis TRESNADO, Antonino II MILANES, Ming Koon ANG, Kian Soo LIM, Mauro Jr. DIONISIO, Teddy Joaquin CARREON
  • Patent number: 10566369
    Abstract: A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 18, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Tim Thian Hwee Tan, Boon Pek Liew, Chee Kay Chow, Teddy Joaquin Carreon
  • Publication number: 20180182801
    Abstract: A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 28, 2018
    Inventors: Tim Thian Hwee TAN, Boon Pek LIEW, Chee Kay CHOW, Teddy Joaquin CARREON