Patents by Inventor Tee-Eu Jin

Tee-Eu Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8546936
    Abstract: A substrate surface of a semiconductor package, comprising: a plurality of product forming areas to provide mounting spaces of semiconductor chips. The substrate surface also comprises a plurality of staggered offset mesh block areas surrounding the plurality of product forming areas. The plurality of staggered offset mesh block areas minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: October 1, 2013
    Assignee: Spansion LLC
    Inventors: Pakhorudin Hussin, Murugasan Manikam Achari, Tee-Eu Jin, Kwet Nam Wong
  • Publication number: 20100258705
    Abstract: A substrate surface of a semiconductor package, comprising: a plurality of product forming areas to provide mounting spaces of semiconductor chips. The substrate surface also comprises a plurality of staggered offset mesh block areas surrounding the plurality of product forming areas. The plurality of staggered offset mesh block areas minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.
    Type: Application
    Filed: June 18, 2010
    Publication date: October 14, 2010
    Inventors: Pakhorudin HUSSIN, Murugasan Manikam ACHARI, Tee-Eu JIN, Kwet Nam WONG
  • Patent number: 7759171
    Abstract: A method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package is disclosed. In one embodiment, a method includes forming a dam structure on an outer area of a substrate surface of a semiconductor package and blocking a flow of a mold material from a mold cavity of the semiconductor package to the outer area of the substrate surface using the dam structure. In another embodiment, a substrate surface of a semiconductor package includes product forming areas to provide mounting spaces of semiconductor chips and staggered offset mesh block areas surrounding the product forming areas to act as dam structures to minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: July 20, 2010
    Assignee: Spansion LLC
    Inventors: Pakhorudin Hussin, Murugasan Manikam Achari, Tee-Eu Jin, Kwet Nam Wong
  • Publication number: 20090057883
    Abstract: A method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package is disclosed. In one embodiment, a method includes forming a dam structure on an outer area of a substrate surface of a semiconductor package and blocking a flow of a mold material from a mold cavity of the semiconductor package to the outer area of the substrate surface using the dam structure. In another embodiment, a substrate surface of a semiconductor package includes product forming areas to provide mounting spaces of semiconductor chips and staggered offset mesh block areas surrounding the product forming areas to act as dam structures to minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Inventors: Pakhorudin Hussin, Murugasan Manikam Achari, Tee-Eu Jin, Kwet Nam Wong