Abstract: A programmable transistor includes impurity regions to reduce punch-through and soft-write phenomena. In order to provide a fast operation, the impurity regions are arranged with regard to one another so that parasitic capacitances at junctions of impurity regions of mutually opposite conductivity type are minimized. For these purposes, the transistor comprises a charge storage region over a channel region in a main semiconductor zone of a first conductivity type located between a source and a drain of a second conductivity type opposite to the first. A first impurity zone of the first conductivity type, substantially laterally contiguous with the drain, extends into the channel region and is more heavily doped than the main zone. The drain includes a heavily doped third impurity region and a lightly doped second impurity region that lies at least mainly between the third region and the zones.

Abstract: A programmable transistor includes impurity regions to reduce punch-through and soft-write phenomena. In order to provide a fast operation, the impurity regions are arranged with regard to one another so that parasitic capacitances at junctions of impurity regions of mutually opposite conductivity type are minimized. For these purposes, the transistor comprises a charge storage region over a channel region in a main semiconductor zone of a first conductivity type located between a source and a drain of a second conductivity type opposite to the first. A first impurity zone of the first conductivity type, substantially laterally contiguous with the drain, extends into the channel region and is more heavily doped than the main zone. The drain includes a heavily doped third impurity region and a lightly doped second impurity region that lies at least mainly between the third region and the zones.

Abstract: A reduced-temperature two-step silicon deposition performed at different silicon sources is used in forming a composite monosilicon/polysilicon layer (20/24/26) on a body that contains a monosilicon region (10) and an adjoining dielectric regin (12). The first step entails selectively depositing silicon, preferably using dichlorosilane as a CVD silicon source, to grow a first monosilicon layer (20) on exposed monosilicon at an average body temperature less than or equal to 950.degree. C. Substantially no silicon accumulates on exposed dielectric material during the first step. The second step entails non-selectively depositing silicon, preferably using silane as a CVD silicon source, at an average body temperature less than or equal to 950.degree. C. to grow a second monosilicon layer (24) on the first monosilicon layer and to simultaneously grow a polysilicon layer (26) on the exposed dielectric material.

Abstract: In a semiconductor fabrication technique, a first patterned layer (16) of nonmonocrystalline semiconductor material is created on a substructure (10, 12, 14). An insulating layer (22) is thermally grown along the patterned layer in such a way that the upper edge of the remainder (16A) of the patterned layer forms an asperity (24). A blanket layer 26, preferably consisting of nonmonocrystalline semiconductor material, is formed over the insulating layer. Using an etchant that attacks the blanket and patterned layers more than the insulating layer, a selective etch is performed to remove a section of the blanket layer. The etch is continued past the blanket layer to remove the underlying portion of the insulating layer located along the asperity and then, importantly, to remove the so exposed part of the asperity. The remainder (26A) of the blanket overlies the remainder ( (24A) of the asperity.

Abstract: Gate sidewall spacers are created by a two-step procedure in fabricating a field-effect transistor using a protective material such as silicon nitride to prevent gate-electrode oxidation. In the first step, a layer (32) of insulating material is conformally deposited and then substantially removed except for small spacer portions (34) adjoining the sidewalls of a doped non-monocrystalline semiconductor layer (20A) destined to become the gate electrode (36). The second step consists of performing an oxidizing heat treatment to increase the thickness of the spacer portions. No significant gate dielectric encroachment occurs. Also, the spacers achieve a profile that substantially avoids electrical shorts.

Abstract: A method for fabricating insulated gate field effect transistors in NMOS or CMOS with source and drain regions having lightly doped extensions wherein the source and drain regions are made with a self-aligned process and a device made in accordance with such a method.

Abstract: In an improved method for growing an oxide layer on a silicon surface of a semiconductor body, the semiconductor body is first provided with a silicon surface. A first oxide layer portion is then grown over the silicon surface in a first thermal oxidation process at a temperature of less than about 1000.degree. C. The semiconductor device is then annealed in a nonoxidizing ambient at a temperature above about 1000.degree. C., and finally a second oxide layer portion is then grown over the first oxide layer portion in a second thermal oxidation process to complete the growth of the oxide layer. The silicon surface may be of either polycrystalline or monocrystalline material. This method avoids both the dopant outdiffusion problems associated with present high-temperature oxidation processes and the stress-related irregularities associated with known low-temperature oxidation processes.