Abstract: RNA molecules for RNA interference to target a mutant allele with a point mutation, wherein the molecule has a nucleotide sequence complementary to a nucleotide sequence of a coding region of the mutant allele; and when counted from the base at the 5?-end in the nucleotide sequence complementary to the sequence of the mutant allele: a base at position 5 or 6 is mismatched with a base in the mutant allele; a base at position 10 or 11 is at the position of the point mutation and is identical to the base at the position of the point mutation in the mutant allele; the group at the 2?-position of the pentose in the ribonucleotide at position 8 is modified with OCH3, halogen, or LNA; and the group at the 2?-position of the pentose in the ribonucleotide at position 7 is not modified with any of OCH3, halogen, and LNA.

Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.

Abstract: The application discloses Lactobacillus strains having a beneficial effect on the metabolic health on a mammalian subject. Further disclosed is compositions comprising such strains and the use thereof for improving the metabolic health or for lowering the blood glucose level in a mammalian subject.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: A brainwave auscultation method includes steps: providing a brainwave auscultation device; placing a brainwave pickup unit of the brainwave auscultation device on the head of a testee to acquire a primitive brainwave signal of the testee, and transmitting the primitive brainwave signal to a signal processing unit; the signal processing unit filtering the primitive brainwave signal according to a waveband reservation standard to generate a preparatory signal, wherein wavebands reserved by the waveband reservation standard include a ? waveband, a ? waveband, an ? waveband, a ? waveband, and a ? waveband; the signal processing unit shifting a central frequency of the preparatory signal to an audible range of human ears; the signal processing unit performing spread-spectrum operation to the shifted preparatory signal to generate a pre-vocalization signal whose frequencies range from 20 Hz to 20 kHz; and making a loudspeaker generate sounds based on the pre-vocalization signal.

Abstract: First and second wires form a wire assembly by being wound around a winding core portion together. The wire assembly includes a twisted wire portion, an inner layer portion, an outer layer portion, a plurality of outward transition portions, and an inward transition portion. The outer layer portion includes a first outer layer portion which is connected to one of the outward transition portions extending from an intermediate position of the inner layer portion and connected to the inward transition portion. The inward transition portion extends to an intermediate position of the inner layer portion.

Abstract: An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.

Abstract: The semiconductor device manufacturing method includes a bonding step of bonding a wire to an electrode (35a), a looping wire formation step of looping the wire from the electrode (35a) to a dummy electrode (34) to form a looping wire (50a), a pressing step of pressing a part of the wire, a moving step of moving the pressed part of the wire directly above the electrode, a wire separation step of separating the wire partially from a wire supply to form a pin wire (55a) extending vertically upward from the electrode (35a), wherein the looping wire formation step adjusts the looping height of the wire to set the length of the looping wire to a predetermined length.

Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.

Abstract: A coil component includes a drum core including a winding core portion and flange portions on opposite sides of the winding core portion in its axial direction, a wire wound around the winding core portion, and a sheet core arranged on a top surface of each of the flange portions and on the wire with an adhesive interposed therebetween. The adhesive contains no filler. A shortest distance between the top surface of the flange portion and the sheet core is not smaller than about 3 ?m.

Abstract: First and second wires form a wire assembly by being wound around a winding core portion together. The wire assembly includes a twisted wire portion, an inner layer portion, an outer layer portion, a plurality of outward transition portions, and an inward transition portion. The outer layer portion includes a first outer layer portion which is connected to one of the outward transition portions extending from an intermediate position of the inner layer portion and connected to the inward transition portion. The inward transition portion extends to an intermediate position of the inner layer portion.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: The present invention relates to a method for producing a chemically strengthened glass substrate, the method including the following steps (A) to (C): (A) preparing a chemically strengthened glass substrate A having a main surface and an end surface; (B) obtaining a glass substrate by polishing a surface of the chemically strengthened glass substrate A; and (C) performing ion exchange by bringing the glass substrate into contact with an inorganic salt composition including 90% by mass or more of KNO3 and 1.0% by mass or more and 6.0% by mass or less of NaNO3 to obtain a chemically strengthened glass substrate C.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: An ink includes a boron-doped nanodiamond having a specific surface area of 110 m2/g or greater, and electrical conductivity at 20° C. of 5.0×10?3 S/cm or greater.

Abstract: A laser treatment apparatus that is configured to irradiate a laser beam to an affected area to treat the affected area. The laser treatment apparatus includes: a beam source device that is configured to output a laser beam; and a scanning device that is configured to scan a therapeutic range including the affected area with the laser beam by irradiating the laser beam to the therapeutic range. The scanning device has a transmission medium that is configured to change an output direction of a laser beam according to an applied voltage.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: Methods and apparatus for forming a patterned layer of material are disclosed. In one arrangement, a deposition-process material is provided in gaseous form. A layer of the deposition-process material is formed on the substrate by causing condensation or deposition of the gaseous deposition-process material. A selected portion of the layer of deposition-process material is irradiated to modify the deposition-process material in the selected portion.

Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.