Patents by Inventor Tei-Wei Kuo

Tei-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130326148
    Abstract: A method for memory management is provided for a memory including a plurality of pages. The method comprises assigning in-use pages to in-use buckets according to use counts. The in-use buckets include a low in-use bucket for a lowest range of use counts, and a high in-use bucket for a highest range of use counts. The method comprises assigning free pages to free buckets according to use counts. The free buckets include a low free bucket for a lowest range of use counts, and a high free bucket for a highest range of use counts. The method maintains use counts for in-use pages. On a triggering event for a current in-use page, the method determines whether the use count of the current in-use page exceeds a hot swap threshold, and if so moves data in the current in-use page to a lead page in the low free bucket.
    Type: Application
    Filed: October 5, 2012
    Publication date: December 5, 2013
    Inventors: Po-Chao Fang, Cheng-Yuan Wang, Hsiang-Pang Li, Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo
  • Patent number: 8392690
    Abstract: A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: March 5, 2013
    Assignee: Genesys Logic, Inc.
    Inventors: Yuan-sheng Chu, Jen-wei Hsieh, Yuan-hao Chang, Tei-wei Kuo, Cheng-chih Yang
  • Patent number: 8356136
    Abstract: A block management method applicable to a non-volatile memory storage system is provided. The non-volatile memory storage system includes a plurality of chips. Each chip includes a plurality of physical blocks. The physical blocks form a plurality of physical block sets. Each logical block in a logical space corresponds to at most two physical block sets. In the block management method, when a logical block corresponds to two physical block sets filled with data and more data is to be written, a free physical block set is allocated for storing the data. Then, one of the two physical block sets corresponding to the logical block is selected according to a predetermined criterion. The valid data in the selected physical block set is copied into the free physical block set. Next, the selected physical block set is erased and collected to the pool of free physical block sets.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: January 15, 2013
    Assignee: National Taiwan University
    Inventors: Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 8341336
    Abstract: A region-based management method of a non-volatile memory is provided. In the region-based management method, the storage space of all chips in the non-volatile memory is divided into physical regions, physical block sets, and physical page sets, and a logical space is divided into virtual regions, virtual blocks, and virtual pages. In the non-volatile memory, each physical block set is the smallest unit of space allocation and garbage collection, and each physical page set is the smallest unit of data access. The region-based management method includes a three-level address translation architecture for converting logical block addresses into physical block addresses.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: December 25, 2012
    Assignee: National Taiwan University
    Inventors: Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 8204917
    Abstract: An intermediary apparatus, an intermediary method, and a computer program product thereof for storing data in a storage apparatus, and a data storage system comprising the same are provided. The storage apparatus has a storage zone with a signature field, and the signature field stores a first signature value. The data has index information and a data signature value. After searching out the storage zone according to the index information, the intermediary apparatus extracts the first signature value from the storage zone, and then determines if the data has been stored in the storage zone according to the first signature value and the data signature value. If not, the intermediary apparatus writes the data into the storage zone; otherwise, ignores the data.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: June 19, 2012
    Assignee: Institute for Information Industry
    Inventors: Da-Gang Lee, Hung-Jyun Mu, Chun-Sho Lee, Tei-Wei Kuo, Pei-Lun Suei, Rong-Jhang Liao, Yung-Feng Lu
  • Publication number: 20110235636
    Abstract: A mobile ad hoc network (MANET) and a method for establishing a routing thereof are provided. The MANET includes a plurality of nodes. Each node determines a corresponding parent node according to a request packet resource of a request packet and a node resource of each node, so as to establish transmission routes between the nodes. Furthermore, needless transmission route is eliminated by the node belonging to a multicast group according to a group table of each node.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 29, 2011
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Pi-Cheng Hsiu, Tei-Wei Kuo, Ai-Chun Pang, Yung-Chih Liu, Chun-Wei Chou
  • Patent number: 8010876
    Abstract: A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-correcting operation on the write-in data and the extra data. Finally, store the N write-in data and the generated K extra data into the data area and the first ECC into the spare area. During read process, the present invention utilizes the steps of reading data from the data area of the target flash-memory page to generate the second ECC, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data. The higher the counter values, the lower the likelihood the corresponding bit is selected to be retrieved.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 30, 2011
    Assignee: Genesys Logic, Inc.
    Inventors: Jen-wei Hsieh, Tei-wei Kuo, Hsiang-chi Hsieh
  • Patent number: 8010770
    Abstract: A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: August 30, 2011
    Assignee: Genesys Logic, Inc.
    Inventors: Chin-hsien Wu, Tei-wei Kuo, Hsiang-Chi Hsieh
  • Patent number: 7975095
    Abstract: A cache device comprises a hard disk, cache control unit and at least one flash memory, whereby the cache control unit controlling and regulating the flash memory as the hard disk cache device. The present invention method is defined by setting up a management table to manage each corresponding logical block address of the flash memory through a cache data read-out step and cache data write-in step in order to manage the cache read or write action of the flash memory on the hard disk. In addition, the step of recycling a cache space and replacing cache temporary data storage is to remove and replace temporary cache and storage space within the flash memory on the hard disk. Moreover, the step of reconstruction management table is provided to reconstruct management table loss or damage caused by power outage or irregular shut-down of the computer and will be able to provide flash memory on the hard disk cache control.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: July 5, 2011
    Assignee: Genesys Logic, Inc.
    Inventors: Jen-Wei Hsieh, Po-Liang Wu, Yuan-Hao Chang, Tei-Wei Kuo, Cheng-Chih Yang
  • Publication number: 20110161563
    Abstract: A block management method applicable to a non-volatile memory storage system is provided. The non-volatile memory storage system includes a plurality of chips. Each chip includes a plurality of physical blocks. The physical blocks form a plurality of physical block sets. Each logical block in a logical space corresponds to at most two physical block sets. In the block management method, when a logical block corresponds to two physical block sets filled with data and more data is to be written, a free physical block set is allocated for storing the data. Then, one of the two physical block sets corresponding to the logical block is selected according to a predetermined criterion. The valid data in the selected physical block set is copied into the free physical block set. Next, the selected physical block set is erased and collected to the pool of free physical block sets.
    Type: Application
    Filed: February 8, 2010
    Publication date: June 30, 2011
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Yuan-Hao Chang, Tei-Wei Kuo
  • Publication number: 20110161562
    Abstract: A region-based management method of a non-volatile memory is provided. In the region-based management method, the storage space of all chips in the non-volatile memory is divided into physical regions, physical block sets, and physical page sets, and a logical space is divided into virtual regions, virtual blocks, and virtual pages. In the non-volatile memory, each physical block set is the smallest unit of space allocation and garbage collection, and each physical page set is the smallest unit of data access. The region-based management method includes a three-level address translation architecture for converting logical block addresses into physical block addresses.
    Type: Application
    Filed: February 8, 2010
    Publication date: June 30, 2011
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Yuan-Hao Chang, Tei-Wei Kuo
  • Publication number: 20110119280
    Abstract: A candidate key retrieving apparatus, a candidate key retrieving method and a tangible machine-readable medium thereof are provided. The candidate key retrieving apparatus comprises a storage unit and a microprocessor. The storage unit is configured to store a table recording a data amount of the table, a plurality of attributes, and a data distinct amount and a data type of each attribute. The microprocessor is configured to generate a candidate key according to the data amount, the distinct amounts and the data types.
    Type: Application
    Filed: November 30, 2009
    Publication date: May 19, 2011
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Tei-Wei KUO, Chi-Sheng SHIH, Ren-Shan LUOH, Pei-Lun SUEI, Che-Wei KUO, Min-Siong LIANG
  • Publication number: 20110107056
    Abstract: A method for determining data correlation and a data processing method for a memory are disclosed. The data with correlation is collected and stored in the same block. Also the data with correlation is determined based on a specific function to be executed by the user. In other words, if the user needs to access some data in order to perform the specific function, those data has correlation.
    Type: Application
    Filed: September 24, 2010
    Publication date: May 5, 2011
    Applicant: ACER INCORPORATED
    Inventor: Tei-Wei Kuo
  • Publication number: 20110093486
    Abstract: A relational database query system for a relational database is provided, wherein the relational database comprises several relational tables including at least one constant table storing several unique data. The relational database query system comprises a query receiving module for receiving an extensible-markup-language query (XML query); at least a constant mapping tree respectively corresponds to one of the at least constant tables, wherein the at least constant mapping tree comprises several tree nodes respectively with node numbers respectively corresponding to the unique data in the at least constant table; a query generator for converting the XML query to be a structured query language (SQL) query according to the at least constant mapping tree; a query module for querying the relational database with the SQL query.
    Type: Application
    Filed: March 3, 2010
    Publication date: April 21, 2011
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Chuo-Yen Lin, Yung-Feng Lu, Pei-Lun Suei, Shih-Chun Chou, Tei-Wei Kuo
  • Patent number: 7917832
    Abstract: An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and the address register are connected to a flash memory respectively for storing the access instructions and the addresses. The flash memory control circuit is connected to both instruction register and address register for controlling the access to the flash memory. The data register is connected to flash memory control circuit for loading data to be written to the flash memory. The encoder encodes the written data, and the ECC generator generates an ECC, which is written to the flash memory through the signal converter. The comparator and the arbitrator provide the comparison with ECC and informing decoder f suspicious bit values when data is read from the flash memory.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: March 29, 2011
    Assignee: Genesys Logic, Inc.
    Inventors: Jen-Wei Hsieh, Tei-Wei Kuo, Hsiang-Chi Hsieh
  • Patent number: 7890693
    Abstract: A flash translation layer apparatus is disclosed. The flash translation layer apparatus coupled to a flash memory and a reading and writing controller, respectively. The flash translation layer apparatus includes an instruction register, a logical address register, a data register, a first auxiliary controller, a microprocessor, an address converting unit, a second auxiliary controller, a flash address register and an adjustable translation layer unit. Furthermore, the adjustable translation layer unit regards the block as a unit for a coarse-grained address translation table and regards the pages as a unit for a fine-grained address translation table, respectively. Therefore, the present invention can provide capabilities of reducing the spaces and the times of a null data collection procedure and increasing the efficiency when a logical address corresponds to a physical address.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: February 15, 2011
    Assignee: Genesys Logic, Inc.
    Inventors: Cheng-chih Yang, Tei-wei Kuo, Chin-hsien Wu
  • Patent number: 7861028
    Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: December 28, 2010
    Assignee: Genesys Logic, Inc.
    Inventors: Yi-Lin Tsai, Tei-Wei Kuo, Jen-Wei Hsieh, Yuan-Hao Chang, Hsiang-Chi Hsieh
  • Patent number: 7761648
    Abstract: A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The caching mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: July 20, 2010
    Assignee: Genesys Logic, Inc.
    Inventors: Chin-hsien Wu, Tei-wei Kuo, Hsiang-chi Hsieh
  • Publication number: 20100098038
    Abstract: A deploy apparatus, method and computer program product thereof for a wireless network are provided. The wireless network comprises at least one first network node and a second network node. The method comprises the following steps: calculating an output constant and a node constant according to a first default value, a second default value and a third default value; calculating a first evaluation function according to the related information of the network nodes of the wireless network; moving or removing the second network node from the wireless network when the output constant is smaller than one and a test value is smaller than the node constant; calculating a second evaluation function according to the related information of the network nodes of the wireless network; and deploying the wireless network after comparing the first evaluation function and the second evaluation function.
    Type: Application
    Filed: January 15, 2009
    Publication date: April 22, 2010
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jiun-Jian CHANG, Pi-Cheng HSIU, Tei-Wei KUO, Hua-Wei FANG, David M. Di
  • Publication number: 20100023535
    Abstract: An intermediary apparatus, an intermediary method, and a computer program product thereof for storing data in a storage apparatus, and a data storage system comprising the same are provided. The storage apparatus has a storage zone with a signature field, and the signature field stores a first signature value. The data has index information and a data signature value. After searching out the storage zone according to the index information, the intermediary apparatus extracts the first signature value from the storage zone, and then determines if the data has been stored in the storage zone according to the first signature value and the data signature value. If not, the intermediary apparatus writes the data into the storage zone; otherwise, ignores the data.
    Type: Application
    Filed: August 25, 2008
    Publication date: January 28, 2010
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Da-Gang Lee, Hung-Jyun Mu, Chun-Sho Lee, Tei-Wei Kuo, Pei-Lun Suei, Rong-Jhang Liao, Yung-Feng Lu