Abstract: The invention relates to a substrate for a liquid crystal display that forms a part of a display of an information apparatus and a liquid crystal display having the same. The invention provides a substrate for a liquid crystal display which contributes to suppression of an increase in the number of manufacturing steps and an increase in a manufacturing cost and which improves the yield of manufacture, a liquid crystal display having the same, and a method of manufacturing the same.

Abstract: The invention relates to a substrate for a liquid crystal display that forms a part of a display of an information apparatus and a liquid crystal display having the same. The invention provides a substrate for a liquid crystal display which contributes to suppression of an increase in the number of manufacturing steps and an increase in a manufacturing cost and which improves the yield of manufacture, a liquid crystal display having the same, and a method of manufacturing the same.

Abstract: The invention relates to a substrate for a liquid crystal display that forms a part of a display of an information apparatus and a liquid crystal display having the same. The invention provides a substrate for a liquid crystal display which contributes to suppression of an increase in the number of manufacturing steps and an increase in a manufacturing cost and which improves the yield of manufacture, a liquid crystal display having the same, and a method of manufacturing the same.

Abstract: The invention relates to a substrate for a liquid crystal display that forms a part of a display of an information apparatus and a liquid crystal display having the same. The invention provides a substrate for a liquid crystal display which contributes to suppression of an increase in the number of manufacturing steps and an increase in a manufacturing cost and which improves the yield of manufacture, a liquid crystal display having the same, and a method of manufacturing the same.

Abstract: A thin film transistor matrix device comprises a transparent insulating substrate, a thin film transistor unit, a picture element unit, a storage capacitance unit, a gate terminal unit, and a drain terminal unit, the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode; a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode through a contact hole opened in a protecting film common with the passivation film.

Abstract: A thin film transistor matrix device comprises a transparent insulating substrate, a thin film transistor unit, a picture element unit, a storage capacitance unit, a gate terminal unit, and a drain terminal unit, the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode; a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode through a contact hole opened in a protecting film common with the passivation film.

Abstract: A method is disclosed of forming a fine pattern on a substrate, in which an etching mask pattern is formed on a layer of material of a pattern to be formed, an overlying layer is deposited on the pattern material layer and the mask pattern, and thereafter, the overlying layer and the pattern material layer are etched by ion etching. This method makes it possible, due to the pattern-widening effect caused by the deposition of the overlying layer and by the use of ion etching, to form a pattern having a gap smaller than 0.5 .mu.m or a contiguous-disk pattern having a period of 2 .mu.m or less by photolithography having a 1 .mu.m resolution. It is also possible to form a pattern adapted to enable an easy planing process, by utilizing a difference in etching rates between the mask pattern and the overlying layer.

Abstract: A process for manufacturing a dual spacing type magnetic bubble memory chip having a thin garnet film, on which a first area is provided with minor loop transmission lines for memorizing bubble information and a second area is provided with major transmission lines for recording or reading out the bubble information. The process comprises forming a first insulative layer (SiO.sub.2) on the garnet film over the first and second areas, forming conductive patterns on the SiO.sub.2 layer, coating the SiO.sub.2 layer and conductive patterns with a second insulative layer of resin (PLOS) and thermosetting the coated insulative layer, removing by etching part of the SiO.sub.2 and PLOS layers, which exist on the first area, forming a third insulative layer (SiO.sub.2) over the whole surface including the first and second areas, and forming the minor loop transmission lines and the major transmission lines on the third insulative layer.

Abstract: A method of forming a pattern of metal elements arranged with very small gaps therebetween on a substrate in magnetic bubble memory devices, semiconductor devices, and the like. In this method, first, a pattern forming layer having metal portions adapted for forming pattern elements and insulating portions for providing the gaps is formed on the substrate, and thereafter the pattern forming layer is processed by using a photolithograhic technique to form the pattern. By using this method, it is possible to form a permalloy propagation pattern with gaps of a size smaller than 1 .mu.m in a magnetic bubble memory device, for example, by using conventional photolithograhic techniques.

Abstract: A method of exposure used to form circuit patterns of a circuit chip of, for example, a magnetic bubble memory device or a semiconductor IC device whose circuit patterns are composed of a plurality of partially different circuit patterns. In this method, a plurality of projections of a single reticle is effected on a substrate as the substrate is moved by predetermined pitch lengths, and it is possible to form circuit patterns which are different from mere combination of the circuit patterns of the reticle.

Abstract: A cylindrical magnetic domain element is disclosed which utilizes a cylindrical magnetic domain (a magnetic bubble) produced by the application of a bias magnetic field to a magnetic sheet of orthoferrite, garnet or the like. Propagation patterns for the cylindrical magnetic domain are composed of a plurality of sets formed on one side of the magnetic sheet and have a multilayer construction with a non-magnetic film of SiO.sub.2 or the like between the layers. This multilayer construction allows for the formation of a propagation pattern having a relatively narrow pattern gap. Further, the propagation pattern is disclosed as having uniaxial magnetic anisotropy, which facilitates the magnetic bubble propagation and ensures retaining of the magnetic bubble.