Abstract: The alpha blending calculator of the invention executes an alpha blending calculation in accordance with digital data X, Y, and .alpha.. The alpha blending calculator includes multiplexers which select one of X or Y in accordance with bits of the digital data .alpha., respectively, and a calculating section for shifting outputs of the multiplexers by a predetermined number of bits, respectively, and for calculating a sum of the shifted outputs. The calculating section includes first level to Nth level adding portions, and an adder connected to the outputs of the Nth level adding portion for executing a multi-bit addition. Each of the first level to the Nth level adding portions receives a plurality of stages of data, classifies the plurality of stages of data into quotient groups and a remainder group, calculates a sum and a carry for each of the quotient groups, and outputs the sum, the carry, and the stages of data in the remainder group to the next level adding portion.

Abstract: Pixel processors each having a depth register, an intensity register and an adder are connected in a linear array. Each pixel processor processes one pixel on a horizontal scan line. A token having plane segment information is shifted in one direction in the array, and each pixel processor updates the registers while it performs hidden surface elimination in a time-division fashion. A refresh token for an intensity data output is also shifted in one direction, and intensity data stored in each pixel processor is supplied to an intensity data bus. A hardware of the pixel processor is very much simplified and LSI implementation is facilitated while maintaining a high image output rate.

Abstract: The interconnection chip of the present invention is a custom chip which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports. The chip includes a crossbar interconnection, a FIFO or programmable delay for each of its inputs and a pipeline register file for each of its outputs. By using pre-stored control patterns, the chip can configure its crossbar and delays while performing other operations. Therefore, the usual functions of busses and register files can be realized with this single chip. Various embodiments and applications for the chip are disclosed.