Patents by Inventor Teijun Dai

Teijun Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bias circuit for use with divided bit lines
    Patent number: 10819936
    Abstract: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 27, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hiroaki Ebihara, Zheng Yang, Rui Wang, Teijun Dai
  • BIAS CIRCUIT FOR USE WITH DIVIDED BIT LINES
    Publication number: 20200260031
    Abstract: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 13, 2020
    Inventors: Hiroaki Ebihara, Zheng Yang, Rui Wang, Teijun Dai