Abstract: An integrated device package is disclosed. The integrated device package can include a substrate that has a first side and a second side, an electronic component that is mounted on the first side or the second side of the substrate, a molding material that is disposed at least on the first side of the substrate, and an conductive material that is disposed on the first side of the substrate and extending through the molding material. The molding material has an exterior surface facing away from the substrate. The exterior surface of the molding material includes laser grooves indicative of laser lapping.

Abstract: A package is disclosed. The package can include a package substrate that has an opening, such as a through hole, extending from a top side to a bottom side opposite the top side of the package substrate. The package can also include a component at least partially disposed in the through hole. The component can be an electrical component. The component can be exposed at a bottom surface of the package. The package can include a bonding material that mechanically couples the component and the package substrate.

Abstract: A package is disclosed. The package includes a substrate and an electrical component vertically mounted to the substrate. The electrical component has a first end, a second end vertically spaced from the first end, and a side wall extending from the first end to the second end. The first end of the electrical component is positioned between the substrate and the second end of the electrical component. The package can also include a molding material disposed at least partially along the side wall of the electrical component.

Abstract: A package is disclosed. The package can include a package substrate that has an opening, such as a through hole, extending from a top side to a bottom side opposite the top side of the package substrate. The package can also include a component at least partially disposed in the through hole. The component can be an electrical component. The component can be exposed at a bottom surface of the package. The package can include a bonding material that mechanically couples the component and the package substrate.

Abstract: A multi-package unit having stacked packages is provided. A multi-package unit may include a first package and a second package mounted on the first package. The first package may be a leadframe package that includes metal leads extending beyond the perimeter of the first package. The first package may include a first integrated circuit die assembled within the first package using the wirebond configuration or the flip-chip configuration. The second package may be a leadframe package or a leadless package that includes a second integrated circuit die. The second package may be smaller than the first package. The first and second integrated circuit dies may be formed using different integrated circuit fabrication technologies.

Abstract: An integrated circuit (IC) package that includes a lead frame, and a die affixed to a first surface of a pad of the lead frame. The die is wire bonded to the lead frame. The package includes a heat sink spaced apart from a second surface of the pad, where the second surface opposes the first surface. Molding compound encapsulates the lead frame and the die. The molding compound is disposed between the heat sink and the second surface of the pad and is enabled access between the heat sink and the second surface through protruding features disposed on the heat sink, the second surface, and/or some combination of the two.

Abstract: Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.

Abstract: In an exemplary embodiment, a method takes as an input a package substrate on which multiple capacitors have been mounted in a ring as part of a design to effectuate on-package decoupling. The method involves plasma cleaning the package substrate and the capacitors to remove organic contaminants. The method then involves applying a thermoset plastic to encase the capacitors on the package substrate. In one embodiment, a heated metal mold is utilized and the thermoset plastic is placed therein. The method includes opening the metal mold and curing the molded thermoset plastic by baking the molded thermoset plastic at an elevated temperature.

Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.

Abstract: Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.

Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.

Abstract: An integrated circuit (IC) package that includes a lead frame, and a die affixed to a first surface of a pad of the lead frame. The die is wire bonded to the lead frame. The package includes a heat sink spaced apart from a second surface of the pad, where the second surface opposes the first surface. Molding compound encapsulates the lead frame and the die. The molding compound is disposed between the heat sink and the second surface of the pad and is enabled access between the heat sink and the second surface through protruding features disposed on the heat sink, the second surface, and/or some combination of the two.

Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.

Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.