Patents by Inventor Teik Wah Lim
Teik Wah Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126228Abstract: Systems or methods of the present disclosure may provide for implementing design software that is used to design a configuration for a programmable fabric of a programmable logic device. Implementing the design software includes receiving, at a processor, design configuration details for the configuration. Implementing the design software also includes receiving, at the processor, a plurality of constraints including a thermal constraint for the configuration. Moreover, implementing the design software comprises performing thermal aware resource selection based at least in part on the thermal constraint. Furthermore, implementing the design software includes causing the programmable logic device to be operated to stay within the thermal constraint.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Inventors: Archanna Srinivasan, Teik Wah Lim, Pravin Chander Chandran
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Publication number: 20240027279Abstract: A method is provided for thermally monitoring an integrated circuit during operation of the integrated circuit. The method includes receiving a measurement of a temperature in a circuit design for the integrated circuit from a temperature sensor, and determining a hottest temperature in the circuit design based on the measurement of the temperature. A non-transitory computer readable storage medium includes computer readable instructions stored thereon for causing a computing system to receive a measurement of a first temperature in a circuit design for an integrated circuit from a temperature sensor, and determine a second temperature of a cold spot in an active region of the circuit design by adjusting the measurement of the first temperature generated by the temperature sensor by an offset.Type: ApplicationFiled: September 28, 2023Publication date: January 25, 2024Applicant: Intel CorporationInventors: Krishnakumar Varadarajan, Aurelien Mozipo, Juan Cevallos Palomeque, Teik Wah Lim, Aanandh Balasubramanian
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Publication number: 20230037609Abstract: Examples described herein relate to an interface and a network interface device coupled to the interface and comprising circuitry to: control power utilization by a first set of one or more devices based on power available to a system that includes the first set of one or more devices, wherein the system is communicatively coupled to the network interface and control cooling applied to the first set of one or more devices.Type: ApplicationFiled: September 28, 2022Publication date: February 9, 2023Inventors: Paniraj GURURAJA, Navneeth JAYARAJ, Mahammad Yaseen Isasaheb MULLA, Nitesh GUPTA, Hemanth MADDHULA, Laxminarayan KAMATH, Jyotsna BIJAPUR, Delraj Gambhira DAMBEKANA, Vikrant THIGLE, Amruta MISRA, Anand HARIDASS, Rajesh POORNACHANDRAN, Krishnakumar VARADARAJAN, Sudipto PATRA, Nikhil RANE, Teik Wah LIM
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Publication number: 20220215147Abstract: An integrated circuit system includes a temperature sensor circuit that generates an output indicative of a temperature in an integrated circuit. The integrated circuit system also includes a temperature management controller circuit that compares the temperature indicated by the output of the temperature sensor circuit to a temperature threshold. The integrated circuit system further includes temperature reduction circuitry and/or design compilation techniques and partial or full reconfiguration that controls the temperature in the integrated circuit system. The temperature management controller circuit causes the temperature reduction circuitry to reduce the temperature in response to the temperature indicated by the output of the temperature sensor circuit exceeding the temperature threshold. The temperature sensor circuit, the temperature management controller circuit, and the temperature reduction circuitry may be implemented by soft logic circuits, hard logic circuits, or any combination thereof.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Applicant: Intel CorporationInventors: Teik Wah Lim, Rajiv Mongia, Archanna Srinivasan, Mahesh A. Iyer
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Patent number: 10530367Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.Type: GrantFiled: December 28, 2018Date of Patent: January 7, 2020Assignee: Intel CorporationInventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
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Publication number: 20190140647Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
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Patent number: 10164517Abstract: A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic signal having a periodic signal frequency as a variable. The periodic signal frequency may be tuned to reduce impedance, jitter, or noise.Type: GrantFiled: August 17, 2016Date of Patent: December 25, 2018Assignee: ALTERA CORPORATIONInventors: Teik Wah Lim, Ashraf Lotfi
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Patent number: 10103627Abstract: A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.Type: GrantFiled: February 26, 2015Date of Patent: October 16, 2018Assignee: Altera CorporationInventors: Teik Wah Lim, Ashraf W. Lotfi, Choong Kit Wong, John Weld
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Publication number: 20180054110Abstract: A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic signal having a periodic signal frequency as a variable. The periodic signal frequency may be tuned to reduce impedance, jitter, or noise.Type: ApplicationFiled: August 17, 2016Publication date: February 22, 2018Inventors: Teik Wah Lim, Ashraf Lotfi
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Publication number: 20160254745Abstract: A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.Type: ApplicationFiled: February 26, 2015Publication date: September 1, 2016Applicant: ALTERA CORPORATIONInventors: Teik Wah Lim, Ashraf W. Lotfi, Choong Kit Wong, John Weld
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Patent number: 8659334Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: GrantFiled: July 6, 2012Date of Patent: February 25, 2014Assignee: Altera CorporationInventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
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Patent number: 8327305Abstract: A circuit and methods for placing a circuit block on an integrated circuit (IC) are disclosed. An embodiment of the disclosed method includes dividing the IC into multiple regions based on pre-determined value. This pre-determined value may be a voltage drop value measured on specific regions on the IC. The performance requirement for the circuit block is determined and placed in one of the regions on the IC. In one embodiment, the placement of the circuit block is based on the performance requirement and the measured value at specific regions on the IC. The measured value may be a voltage drop value and a circuit block with a higher performance may be placed in a region with a lower voltage drop value.Type: GrantFiled: July 31, 2009Date of Patent: December 4, 2012Assignee: Altera CorporationInventors: Woi Jie Hooi, Teik Wah Lim, Ket Chiew Sia
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Publication number: 20120274375Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: ApplicationFiled: July 6, 2012Publication date: November 1, 2012Inventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
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Patent number: 8232823Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: GrantFiled: June 5, 2009Date of Patent: July 31, 2012Assignee: Altera CorporationInventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan