Abstract: Embodiments of a multicarrier receiver and method for generating soft bits in a multiple-input multiple-output system are generally described herein. In some embodiments, operational parameters for an equalizer and a soft-bit demapper in a multicarrier receiver are determined. Other embodiments may be described and claimed.

Abstract: A method for formatting ATM cells compliant with SPI-4 Phase 2 specification is presented. The method enables selection among various cell formats depending on the devices employed, and enables use of a payload-only test format, a typical format having payload and header data, a format having header error correction (HEC) data and dummy data, and a format having HEC data and user data.

Abstract: Embodiments of a MIMO receiver and method for beamforming using CORDIC operations are generally described herein. Other embodiments may be described and claimed. In some embodiments, complex singular value decomposition (SVD) operations are performed on a channel matrix using CORDIC operations to generate vector elements of a beamforming matrix. An inner product of a first of the vector elements and each of a plurality of stored codewords is computed using CORDIC operations. A recursive dimensional reduction on the beamforming matrix is performed based on the quantized first vector element is performed using CORDIC operations. In some embodiments, the MIMO receiver includes reprogrammable CORDIC circuitry.

Abstract: Embodiments of a MIMO receiver and method for beamforming using CORDIC operations are generally described herein. Other embodiments may be described and claimed. In some embodiments, complex singular value decomposition (SVD) operations are performed on a channel matrix using CORDIC operations to generate vector elements of a beamforming matrix. An inner product of a first of the vector elements and each of a plurality of stored codewords is computed using CORDIC operations. A recursive dimensional reduction on the beamforming matrix is performed based on the quantized first vector element is performed using CORDIC operations. In some embodiments, the MIMO receiver includes reprogrammable CORDIC circuitry.

Abstract: A converter or a resampler used in a digital communication system converts a first digital signal representing an analog signal into a second digital signal representing the same analog signal. The converter includes a converter filter and a timing circuit. The timing circuit provides a first clock generated from a second clock, and a phase control signal for controlling the conversion of the converter filter. The timing circuit is preferably a numerical controlled oscillator (NCO) and includes an accumulator for generating the first clock from the second clock and a phase offset, and a phase calculator which receives the phase offset to generate a phase control signal. The phase control signal includes a plurality of phase weighting signals, a plurality of control signals, and an interpolation signal. The first digital signal is selectively convoluted with the phase weighting signals, which is controlled by the control signals.

Abstract: Level trigger mode interrupts are converted to edge trigger mode interrupts in a computer system. A circuit detects the occurrence of a level trigger mode interrupt request, and asserts an edge trigger mode interrupt request output. The edge trigger mode interrupt request remains asserted until an End of Interrupt input is asserted, indicating that the CPU has completed servicing the prior interrupt. The edge trigger mode interrupt request is then deasserted.

Abstract: A method and system for testing a digital counter of mn bits comprises dividing the counter into m segments, each of n bits. For test purposes, the counter then is further divided into first and second m segment groups. Multiplex gates are used between the segments and are controlled by sensing the condition of the most significant bits of the most significant one of the m segments for applying clock pulses to verify specific connections between various bits of the counter for the first four cycles of clock pulses applied during the test mode. After these four cycles, gating circuits coupled with the most significant bits of the most significant one of the m segments are used to automatically switch the remainder of the test connections to the second group to verify all of the remaining connections in the counter, with full testing of the counter being accomplished in 2.sup.n +2 cycles of clock pulses.

Abstract: A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount.