Patents by Inventor Teja Singh

Teja Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10924120
    Abstract: An oscillator circuit includes a phase-locked loop (PLL) with a plurality of voltage controlled oscillator (VCO), a clock divider circuit receiving the VCO phase outputs and outputting a first stage clock signal with an adjustable clock period related to the PLL period based on selecting a combination of two of the VCO phase outputs. The first stage clock signal has a balanced duty cycle at frequencies that are related to the PLL frequency by even fractional divisions of the VCO phase output period based on the quantity VCO phase outputs, and an unbalanced duty cycle at frequencies that are related by odd fractional divisions. A duty cycle adjustment (DCA) circuit receives the first stage clock signal selectively adjusts a falling edge of the first stage clock signal to provide an even duty cycle and feeds a resulting signal to the second stage clock signal output.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Samiul Haque Khan, Vibhor Mittal, Shravan Lakshman, Teja Singh
  • Patent number: 8947124
    Abstract: An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 3, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Teja Singh, Sundar Rangarajan
  • Publication number: 20140232431
    Abstract: An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 21, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Teja Singh, Sundar Rangarajan
  • Patent number: 6766498
    Abstract: A method, system and computer program product for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit. A selected number of interconnections in an integrated circuit may be identified (“interconnections of interest”). A netlist containing a list of the transistors in the integrated circuit may be pruned by selecting those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest. Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted. These extracted parasitic resistance and capacitance values may be associated with the transistors connected to those layout layers in the pruned netlist.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mahesh S. Sharma, David M. Newmark, Teja Singh, Joshua A. Bell
  • Publication number: 20040044974
    Abstract: A method, system and computer program product for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit. A selected number of interconnections in an integrated circuit may be identified (“interconnections of interest”). A netlist containing a list of the transistors in the integrated circuit may be pruned by selecting those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest. Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted. These extracted parasitic resistance and capacitance values may be associated with the transistors connected to those layout layers in the pruned netlist.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 4, 2004
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mahesh S. Sharma, David M. Newmark, Teja Singh, Joshua A. Bell