Patents by Inventor Tejas Karkhanis

Tejas Karkhanis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR
    Publication number: 20110320765
    Abstract: A computer processor, method, and computer program product for executing vector processing instructions on a variable width vector register file. An example embodiment is a computer processor that includes an instruction execution unit coupled to a variable width vector register file which contains a number of vector registers, the width of the vector registers is changeable during operation of the computer processor.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 29, 2011
    Applicant: International Business Machines Corporation
    Inventors: Tejas Karkhanis, Jose E. Moreira, Valentina Salapura
  • Architectural Level Throughput Based Power Modeling Methodology and Apparatus for Pervasively Clock-Gated Processor Cores
    Publication number: 20080027664
    Abstract: A method for estimating power dissipated by a processor core processing a workload-includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 31, 2008
    Inventors: Pradip Bose, Tejas Karkhanis, Srinivasan Ramani, Malcolm Ware, Ken Vu
  • Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
    Publication number: 20060080625
    Abstract: A method, system, and apparatus for estimating the power dissipated by a processor core processing a workload, where the method includes analyzing a reference test case to generate a reference workload characteristic. Analyzing an actual workload to generate an actual workload characteristic. Performing a power analysis for the reference test case to establish a reference power dissipation value.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 13, 2006
    Inventors: Pradip Bose, Tejas Karkhanis, Srinivasan Ramani, Malcolm Ware, Ken Vu