Patents by Inventor Tejas Krishnamohan
Tejas Krishnamohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8767467Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.Type: GrantFiled: August 19, 2013Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventors: Krishna K. Parat, Akira Goda, Koichi Kawal, Brian J. Soderling, Jeremy Binfet, Arnaud A. Furnemont, Tejas Krishnamohan, Tyson M. Stichka, Giuseppina Puzzilli
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Publication number: 20130332769Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.Type: ApplicationFiled: August 19, 2013Publication date: December 12, 2013Applicant: Micron Technology, Inc.Inventors: Krishna K. Parat, Akira Goda, Koichi Kawai, Brian J. Soderling, Jeremy Binfet, Arnaud A. Furnemont, Tejas Krishnamohan, Tyson M. Stichka, Giuseppina Puzzilli
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Patent number: 8514624Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.Type: GrantFiled: June 21, 2011Date of Patent: August 20, 2013Assignee: Micron Technology, Inc.Inventors: Krishna K. Parat, Akira Goda, Koichi Kawai, Brian J. Soderling, Jeremy Binfet, Arnaud A. Furnemont, Tejas Krishnamohan, Tyson M. Stichka, Giuseppina Puzzilli
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Publication number: 20120327713Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Applicant: Micron Technology, Inc.Inventors: Krishna K. Parat, Akira Goda, Koichi Kawai, Brian J. Soderling, Jeremy Binfet, Arnaud A. Furnemont, Tejas Krishnamohan, Tyson M. Stichka, Giuseppina Puzzilli
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Patent number: 8228743Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: GrantFiled: February 10, 2011Date of Patent: July 24, 2012Assignee: Micron Technology, Inc.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A Weimer, Arup Bhattacharyya
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Patent number: 7989289Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.Type: GrantFiled: June 30, 2008Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Tejas Krishnamohan, Krishna Parat, Kyu Min, Srivardhan Gowda, Thomas M. Graettinger, Nirmal Ramaswamy
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Publication number: 20110147827Abstract: The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: Fatma Arzum Simsek-Ege, Sanh Tang, Nirmal Ramaswamy, Thomas M. Graettinger, Kyu S. Min, Tejas Krishnamohan, Srivardhan Gowda
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Publication number: 20110133268Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: ApplicationFiled: February 10, 2011Publication date: June 9, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D.V. Nirmal Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Patent number: 7898850Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: GrantFiled: October 12, 2007Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Patent number: 7728387Abstract: Various semiconductor devices and methods of manufacture are employed. According to an example embodiment of the present invention, a MOS-compatible semiconductor device exhibits high channel mobility and low leakage. The device includes a channel region having a high-mobility strained material layer and a tunneling mitigation layer on the strained material layer to mitigate tunnel leakage. The strained material has a lattice structure that is strained to match the lattice structure of the tunneling mitigation layer. An insulator layer is on the tunneling mitigation layer, and an electrode is over the insulator and adapted to apply a voltage bias to the channel region to switch the device between conductive and nonconductive states. Current is transported in the conductive state as predominantly facilitated via the mobility of the strained material layer, and wherein tunneling current in the nonconductive state is mitigated by the tunneling mitigation layer.Type: GrantFiled: June 12, 2007Date of Patent: June 1, 2010Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Tejas Krishnamohan, Krishna Chandra Saraswat
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Publication number: 20090321809Abstract: Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventors: Nirmal Ramaswamy, Tejas Krishnamohan, Kyu Min, Thomas M. Graettinger
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Publication number: 20090283817Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.Type: ApplicationFiled: June 30, 2008Publication date: November 19, 2009Inventors: Tejas Krishnamohan, Krishna Parat, Kyu Min, Srivardhan Gowda, Thomas M. Graettinger, Nirmal Ramaswamy
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Publication number: 20090097320Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: ApplicationFiled: October 12, 2007Publication date: April 16, 2009Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Publication number: 20090001443Abstract: Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: INTEL CORPORATIONInventors: Tejas Krishnamohan, Krishna Parat, Kyu Min, Rhett T. Brewer, Thomas M. Graettinger, Nirmal Ramaswamy, M. Noel Rocklein