Patents by Inventor Tejasvi Anand

Tejasvi Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11349482
    Abstract: The integrated circuit (IC) described herein lowers the start-up voltage to, for example, 50 mV, compatible for starting a DC-DC converter from a thermoelectric generator (TEG), even with a small temperature gradient. The IC further improves end-to-end efficiency of the energy harvester by improving power efficiency of the DC-DC converter while ensuring maximum power transfer from the TEG at low voltages. The IC uses a low voltage integrated charge pump that can boost sub-100 mV input voltage. A startup clock is generated by a ring-oscillator that begins operation with low supply (e.g., 50 mV or less), and which allows for one inductor to be used for DC-DC converter and for startup of the converter. The IC can be configured between the TEG and any downstream sensor or communication circuits to provide an acceptable (e.g., greater than 1 V) voltage for powering the downstream circuits from a low-voltage (e.g., less than 200 mV) TEG energy source.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 31, 2022
    Assignee: Oregon State University
    Inventors: Soumya Bose, Matthew Johnston, Tejasvi Anand
  • Patent number: 11070129
    Abstract: An ultra-low voltage inverter includes a first inverter, a second inverter, and third inverter. The first inverter receives an input from a delay cell and generates an output for a subsequent delay cell. The second inverter is coupled to the first inverter. The third inverter is coupled to the first inverter, wherein outputs of the second and third inverters are coupled to source terminals of a p-type transistor and an n-type transistor of the first inverter, respectively. The ultra-low voltage inverter forms a delay cell, which is a building block of an ultra-low voltage ring-oscillator. A NAND gate is formed using three inverters such that outputs of two inverters are coupled to the p-type transistors of the NAND gate, while an output of the third inverter of the three inverters is coupled to an n-type transistor of the NAND gate.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: July 20, 2021
    Assignee: Oregon State University
    Inventors: Soumya Bose, Matthew Johnston, Tejasvi Anand
  • Publication number: 20200321862
    Abstract: The integrated circuit (IC) described herein lowers the start-up voltage to, for example, 50 mV, compatible for starting a DC-DC converter from a thermoelectric generator (TEG), even with a small temperature gradient. The IC further improves end-to-end efficiency of the energy harvester by improving power efficiency of the DC-DC converter while ensuring maximum power transfer from the TEG at low voltages. The IC uses a low voltage integrated charge pump that can boost sub-100 mV input voltage. A startup clock is generated by a ring-oscillator that begins operation with low supply (e.g., 50 mV or less), and which allows for one inductor to be used for DC-DC converter and for startup of the converter. The IC can be configured between the TEG and any downstream sensor or communication circuits to provide an acceptable (e.g., greater than 1 V) voltage for powering the downstream circuits from a low-voltage (e.g., less than 200 mV) TEG energy source.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 8, 2020
    Applicant: Oregon State University
    Inventors: Soumya Bose, Matthew Johnston, Tejasvi Anand
  • Publication number: 20200321948
    Abstract: An ultra-low voltage inverter includes a first inverter, a second inverter, and third inverter. The first inverter receives an input from a delay cell and generates an output for a subsequent delay cell. The second inverter is coupled to the first inverter. The third inverter is coupled to the first inverter, wherein outputs of the second and third inverters are coupled to source terminals of a p-type transistor and an n-type transistor of the first inverter, respectively. The ultra-low voltage inverter forms a delay cell, which is a building block of an ultra-low voltage ring-oscillator. A NAND gate is formed using three inverters such that outputs of two inverters are coupled to the p-type transistors of the NAND gate, while an output of the third inverter of the three inverters is coupled to an n-type transistor of the NAND gate.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 8, 2020
    Applicant: Oregon State University
    Inventors: Soumya Bose, Matthew Johnston, Tejasvi Anand
  • Patent number: 10749469
    Abstract: An oscillator includes a first output node and a second output node. There is a tank circuit coupled between the first output node and the second output node. There is a first transistor having a first node, a second node coupled to a current source, and a control node coupled to the second output node. There is a second transistor having a first node, a second node coupled to the current source, and a control node coupled to the first output node. There is a first inductor coupled in series between the first node of the first transistor and the first output node. There is a second inductor coupled in series between the first node of the second transistor and the second output node.
    Type: Grant
    Filed: September 22, 2018
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tejasvi Anand, Mark A. Ferriss, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Publication number: 20190036485
    Abstract: An oscillator includes a first output node and a second output node. There is a tank circuit coupled between the first output node and the second output node. There is a first transistor having a first node, a second node coupled to a current source, and a control node coupled to the second output node. There is a second transistor having a first node, a second node coupled to the current source, and a control node coupled to the first output node. There is a first inductor coupled in series between the first node of the first transistor and the first output node. There is a second inductor coupled in series between the first node of the second transistor and the second output node.
    Type: Application
    Filed: September 22, 2018
    Publication date: January 31, 2019
    Inventors: Tejasvi Anand, Mark A. Ferriss, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Patent number: 10153727
    Abstract: An oscillator includes a first output node and a second output node. There is a tank circuit coupled between the first output node and the second output node. There is a first transistor having a first node, a second node coupled to a current source, and a control node coupled to the second output node. There is a second transistor having a first node, a second node coupled to the current source, and a control node coupled to the first output node. There is a first inductor coupled in series between the first node of the first transistor and the first output node. There is a second inductor coupled in series between the first node of the second transistor and the second output node.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tejasvi Anand, Mark A. Ferriss, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Publication number: 20170331430
    Abstract: An oscillator includes a first output node and a second output node. There is a tank circuit coupled between the first output node and the second output node. There is a first transistor having a first node, a second node coupled to a current source, and a control node coupled to the second output node. There is a second transistor having a first node, a second node coupled to the current source, and a control node coupled to the first output node. There is a first inductor coupled in series between the first node of the first transistor and the first output node. There is a second inductor coupled in series between the first node of the second transistor and the second output node.
    Type: Application
    Filed: May 12, 2016
    Publication date: November 16, 2017
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tejasvi Anand, Mark A. Ferriss, Bodhisatwa Sadhu, Alberto Valdes Garcia