Patents by Inventor Tejaswi Gowda

Tejaswi Gowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230113589
    Abstract: The disclosure concerns biometeorological sensing devices including a processor communicatively coupled to a memory, and a plurality of sensors communicatively coupled to the processor. The plurality of sensors includes a humidity sensor, a UV sensor, an anemometer, an atmospheric thermometer, a globe thermometer, and a camera. The device also includes a network interface communicatively coupled to the processor. The processor is configured to estimate a mean radiant temperature (MRT) using data received from the plurality of sensors, identify a person in an image received from the camera, determine a bounding box that encloses the person in the image, generate a shadow map from the image, calculate an intersection over union (IOU) of the bounding box with the shadow map to determine if the person is in the shade, and transmit observed space usage and estimated MRT to a server communicatively coupled to the network interface.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 13, 2023
    Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Karthik Kashinath Kulkarni, Suren Jayasuriya, Ariane Middel, Tejaswi Gowda, Florian Arwed Schneider
  • Patent number: 8601417
    Abstract: Systems and methods for identifying a Boolean function as either a threshold function or a non-threshold function are disclosed. In one embodiment, in order to identify a Boolean function as either a threshold function or a non-threshold function, a determination is first made as to whether the Boolean function satisfies one or more predefined conditions for being a threshold function, where the one or more predefined conditions include a condition that both a positive cofactor and a negative cofactor of the Boolean function are threshold functions. If the one or more predefined conditions are satisfied, a determination is made as to whether weights for the positive and negative cofactors are equal. If the weights for the cofactors are equal, then the Boolean function is determined to be a threshold function. Further, in one embodiment, this threshold function identification process is utilized in a threshold circuit synthesis process.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: December 3, 2013
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Tejaswi Gowda, Sarma Vrudhula
  • Patent number: 8181133
    Abstract: Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: May 15, 2012
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Tejaswi Gowda, Sarma Vrudhula
  • Publication number: 20110214095
    Abstract: Systems and methods for identifying a Boolean function as either a threshold function or a non-threshold function are disclosed. In one embodiment, in order to identify a Boolean function as either a threshold function or a non-threshold function, a determination is first made as to whether the Boolean function satisfies one or more predefined conditions for being a threshold function, where the one or more predefined conditions include a condition that both a positive cofactor and a negative cofactor of the Boolean function are threshold functions. If the one or more predefined conditions are satisfied, a determination is made as to whether weights for the positive and negative cofactors are equal. If the weights for the cofactors are equal, then the Boolean function is determined to be a threshold function. Further, in one embodiment, this threshold function identification process is utilized in a threshold circuit synthesis process.
    Type: Application
    Filed: April 20, 2011
    Publication date: September 1, 2011
    Applicant: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Tejaswi Gowda, Sarma Vrudhula
  • Publication number: 20090235216
    Abstract: Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 17, 2009
    Applicant: Arizona Board of Regents, a body Corporate of the State of Arizona, Acting for and on Behalf of Ariz
    Inventors: Tejaswi Gowda, Sarma Vrudhula