Patents by Inventor Tejinder Kumar

Tejinder Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10949258
    Abstract: A device includes a first and a second stage round robin arbitrations receiving request signals associated with a first, a second and a third user. At least one request signal for each of the first, the second, and the third user is asserted to access a common resource. The first stage round robin arbitration selects the first, the second, and the third user in a round robin fashion, at a first, a second, and a third iteration. The second stage round robin arbitration receives the user selection and the plurality of request signals and at the first, the second, and the third iteration grants access to the common resource to one request signal associated with the first, the second, and the third user. At each subsequent iteration the first stage round robin arbitration selects a different user and grants access to another request signal until all request signals are processed.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 16, 2021
    Assignee: XILINX, INC.
    Inventors: Tejinder Kumar, Surender Kisanagar
  • Patent number: 10838892
    Abstract: A device includes a first and a second stage round robin arbitrations. The first stage receives request signals and selects a subset the request signals. Each request signal is associated with whether a component is requesting access to a common resource. The second stage receives the selected subset and grants access to the common resource to each request signal of the selected subset that is requesting access, in a round robin fashion. The second stage outputs an enable signal to the first stage when the selected subset is processed. The first stage selects another subset and transmits the selected another subset to the second stage for round robin processing thereof. The process is repeated until all subsets with at least one request signal to access the common resource is processed and granted access in a round robin fashion.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 17, 2020
    Assignee: XILINX, INC.
    Inventor: Tejinder Kumar
  • Patent number: 10572440
    Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 25, 2020
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tejinder Kumar, Rathod Ronak Kishorbhai, Apurva Sen, Rakesh Malik
  • Patent number: 10404278
    Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Rakesh Malik
  • Publication number: 20190197014
    Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Tejinder KUMAR, Rathod RONAK KISHORBHAI, Apurva SEN, Rakesh MALIK
  • Patent number: 10302695
    Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 28, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tejinder Kumar, Akshat Jain
  • Publication number: 20190128960
    Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Tejinder KUMAR, Akshat JAIN
  • Patent number: 10222415
    Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Suchi Prabhu Tandel, Rakesh Malik
  • Patent number: 10198331
    Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Rakesh Malik
  • Publication number: 20180285225
    Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Applicant: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Rakesh Malik
  • Publication number: 20180175883
    Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Applicant: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Rakesh Malik
  • Publication number: 20180164370
    Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 14, 2018
    Applicant: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Suchi Prabhu Tandel, Rakesh Malik
  • Publication number: 20180110196
    Abstract: The invention provides a method for the production of soybean embryogenic callus and somatic embryos. The invention further provides methods of transforming explants that includes generating somatic embryo tissue. The transgenic somatic embryos produced can be used for regenerating stable transgenic plants.
    Type: Application
    Filed: October 18, 2017
    Publication date: April 26, 2018
    Inventors: Sivarama Reddy Chennareddy, Dayakar Pareddy, Tobias M. (Toby) Cicak, Rodrigo Sarria, Katherine K. Effinger, Tejinder Kumar Mall
  • Publication number: 20140173780
    Abstract: A method is disclosed for the Agrobacterium-mediated germline transformation of soybean, comprising infecting split soybean seeds, with a portion of the embryonic axis, with Agrobacterium tumefaciens containing a transgene. The method can further comprise regenerating the explants produced from the transformation of the split soybean seeds comprising a portion of embryonic axis in vitro on selection medium.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 19, 2014
    Inventors: Dayakar Pareddy, Sivarama R. Chennareddy, Tatyana Minnicks, Olga Karpova, David Griffin, Jayakumar P. Samuel, Kelley A. Smith, Rodrigo Sarria-Millan, Tejinder Kumar Mall