Abstract: A series regulator responds to an input voltage to produce a constant direct voltage. A resistor is connected at one end to the output of the regulator. A current carrying bus is connected between the other end of the resistor and the input of the inverter whereby current flows through the resistor producing a voltage drop thereacross and thereafter flows into the inverter to supply power thereto. An electronic switch has a closed position at which current on the bus supplied via the resistor is augmented by the current on the bus supplied via the switch. The switch has an open position at which the augmented current is not present on the bus, the switch being placed in the open position whenever a pulse appears in the control voltage and thereafter is placed in the closed position when the pulse disappears and said voltage drop is at least equal to a preselected value.

Abstract: A signal transmission system which allows digital signals to be transmitted over twisted pair transmission lines. Master and slave transmission circuits are located at the switching system and terminal ends, respectively, of the transmission line. Both circuits include transmit and receive circuitry. The transmit circuitry includes a summing circuit connected to a constant current generator and the receive circuit includes an adaptive equalization/automatic gain control circuit connected between a differential amplifier and a slicer circuit.

Abstract: A signal transmission system which allows digital signals to be transmitted over twisted pair transmission lines. Master and slave transmission circuits are located at the switching system and terminal ends, respectively, of the transmission line. Both circuits include transmit and receive circuitry. The transmit circuitry includes a summing circuit connected to a constant current generator and the receive circuit includes a differential amplifier connected to a slicer circuit.

Abstract: A flip-flop receives clock pulses of frequency F and is alternately set and reset on alternate inverted third clock pulse edges by logic responsive to the clock pulses and to the output of the flip-flop. The logic includes a second flip-flop and a pair of gates which maintain the set and reset states of the first flip-flop for two consecutive clock pulse edges between set and reset transitions to provide symmetrical output pulses from the first flip-flop of frequency 1/3F with a substantially 50% duty cycle.

Abstract: A phase locked loop (10) has a phase insensitive frequency comparator (18) including an up/down counter (26) incremented one way by loop frequency pulses (on 28) and incremented the other way by reference frequency pulses (on 30) and which yields error correction signals (on 22 and 24) to adjust loop frequency when the counter overflows or underflows given limits. Timing means (32) is provided at the input (28, 30) to the counter (26) and prevents any clock pulse from being lost by ensuring a sufficient time gap between pulses. A sample and hold phase detector circuit (16) is provided at the data acquisition input to the loop (10) and enables successful acquisition and lock-on even with many zeros between the incoming data bits, and does so with a minimum number of components.