Abstract: A power supply interruption detecting circuit which prevents an error in a write signal or sending and receiving signals of a data processing unit in the case of interruption of a commercial power supply or a power supply voltage drop resulting from an accident of other units connected to the same power supply. An abrupt drop of the power supply input voltage is detected by comparing the voltage of a CR circuit of a small time constant with the voltage of a CR circuit of a relatively large time constant. A slow input voltage drop is detected by comparing the voltage of the CR circuit of small time constant with a constant reference voltage. The power supply interruption is rapidly detected in substantially a constant short time regardless of input voltage variations and the write signal or the sending and receiving signals are each clamped at predetermined logic voltage, by which sending and writing of an error signal can be effectively prevented.