Patents by Inventor Teng-Chang Chang
Teng-Chang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240048033Abstract: An induction motor with on-rotor slip power recovery may have a rotor and a stator element. The rotor element has a rotor winding system with a number of winding units wound-distributed for inducing a rotor magnetic field. Each winding unit has an induction and an augmentation subwinding. The induction subwinding has two legs of each a number of induction conductor segments. The induction subwinding induces an emf that drives a rotor current in the rotor winding system to generate a basic induction component for the rotor magnetic field when the induction conductor segments move in the stator element. The augmentation subwinding has two legs of each a number of augmentation conductor segments aligned parallel to the induction conductor segments. The augmentation subwinding being wound that the two legs of augmentation conductor segments are immediately next to each other and positioned mid-way between the two legs of induction conductor segments.Type: ApplicationFiled: August 1, 2023Publication date: February 8, 2024Inventors: Pan-Chien LIN, Teng-Chang CHANG
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Publication number: 20190140961Abstract: A quality of service control system includes an input device, a processing unit and an output device. The input device receives a packet. The processing unit obtains an Internet Protocol (IP) version and adds at least one extension column in an undefined IP header, so as to generate a quality of service control packet. The output device transmits the quality of service control packet. Similarly, an input device receives the quality of service control packet and achieves the effect of transmitting the packet with higher priority, determining a transmission rate and keeping data accessed for a specific time according to a packet rate control parameter configuration in the quality of service control packet.Type: ApplicationFiled: December 8, 2017Publication date: May 9, 2019Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Chia-Hong WANG, Teng-Chang CHANG
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Patent number: 9412331Abstract: A display system, an image compensation method and a non-transitory computer readable storage medium thereof are provided. The display system includes a flexible panel, a prediction unit, a compensation unit, an image synthesis unit and a control unit. The prediction unit predicts a prediction angle of the flexible panel in a final time. The compensation unit generates a first compensation image according to an initial display angle of the flexible panel in an initial time, and generates a second compensation image according to the prediction angle. The image synthesis unit synthesizes a first display image according to the first compensation image and the second compensation image. The control unit selectively substitutes the first display image for an image displayed on the flexible panel in the final time.Type: GrantFiled: October 2, 2014Date of Patent: August 9, 2016Assignee: INSTITUTE FOR INFORMATION INDUSTRYInventors: Teng-Chang Chang, Ming-Fang Weng
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Patent number: 9383811Abstract: A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.Type: GrantFiled: November 21, 2011Date of Patent: July 5, 2016Assignee: Institute For Information IndustryInventor: Teng-Chang Chang
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Publication number: 20160042714Abstract: A display system, an image compensation method and a non-transitory computer readable storage medium thereof are provided. The display system includes a flexible panel, a prediction unit, a compensation unit, an image synthesis unit and a control unit. The prediction unit predicts a prediction angle of the flexible panel in a final time. The compensation unit generates a first compensation image according to an initial display angle of the flexible panel in an initial time, and generates a second compensation image according to the prediction angle. The image synthesis unit synthesizes a first display image according to the first compensation image and the second compensation image. The control unit selectively substitutes the first display image for an image displayed on the flexible panel in the final time.Type: ApplicationFiled: October 2, 2014Publication date: February 11, 2016Inventors: Teng-Chang CHANG, Ming-Fang WENG
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Patent number: 9098287Abstract: A super operating system for a heterogeneous computer system for executing tasks of software that has at least one performance processor, a processor supporting logic, and a hypervisor processor. The super operating system has a performance operating system for the performance processor; a hypervisor operating system for the hypervisor processor and a heterogeneous hypervisor software layer on top of the performance and hypervisor processors and below the performance and hypervisor operating systems. Under the super operating system, the hypervisor processor executes tasks that the hypervisor processor has sufficient processing power to handle and puts the performance processor to a power-conserving state. The hypervisor processor brings the performance processor out of power-conserving state to execute tasks that the hypervisor processor has insufficient processing power to handle. The performance and hypervisor processors simultaneously execute tasks that require combined processing power of all processors.Type: GrantFiled: November 21, 2011Date of Patent: August 4, 2015Assignee: Institute For Information IndustryInventor: Teng-Chang Chang
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Publication number: 20120317321Abstract: A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.Type: ApplicationFiled: November 21, 2011Publication date: December 13, 2012Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventor: Teng-Chang CHANG
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Publication number: 20120317571Abstract: A super operating system for a heterogeneous computer system for executing tasks of software that has at least one performance processor, a processor supporting logic, and a hypervisor processor. The super operating system has a performance operating system for the performance processor; a hypervisor operating system for the hypervisor processor and a heterogeneous hypervisor software layer on top of the performance and hypervisor processors and below the performance and hypervisor operating systems. Under the super operating system, the hypervisor processor executes tasks that the hypervisor processor has sufficient processing power to handle and puts the performance processor to a power-conserving state. The hypervisor processor brings the performance processor out of power-conserving state to execute tasks that the hypervisor processor has insufficient processing power to handle. The performance and hypervisor processors simultaneously execute tasks that require combined processing power of all processors.Type: ApplicationFiled: November 21, 2011Publication date: December 13, 2012Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventor: Teng-Chang CHANG
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Publication number: 20120317405Abstract: A method of operating a heterogeneous computer system for executing tasks of software that has at least one performance processor, a processor supporting logic, and a hypervisor processor. The method either i) boots up the hypervisor processor only; or ii) boots up the at least one performance processor after the hypervisor processor; or iii) boots up the at least one performance processor only; or iv) boots up the hypervisor processor after the at least one performance processor. The hypervisor processor executes tasks that the hypervisor processor has sufficient processing power to handle and puts the at least one performance processor to power-conserving state. The hypervisor processor brings the at least one performance processor out of power-conserving state to execute tasks that the hypervisor processor has insufficient processing power to handle. The at least one performance and hypervisor processors simultaneously execute tasks that require combined processing power of all processors.Type: ApplicationFiled: November 21, 2011Publication date: December 13, 2012Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventor: Teng-Chang CHANG
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Publication number: 20120317429Abstract: A green computing heterogeneous computer system for executing software has at least one performance processor, a processor supporting logic supporting the at least one performance processor for executing tasks of the software, and a hypervisor processor that consumes less power than the at least one performance processor. Supported by the processor supporting logic, the hypervisor processor executes tasks of the software that the hypervisor processor has sufficient processing power to handle and puts the at least one performance processor to a power-conserving state. The hypervisor processor brings the at least one performance processor out of idle state to execute tasks of the software that the hypervisor processor has insufficient processing power to handle. The at least one performance and hypervisor processors simultaneously execute tasks of the software that require combined processing power of all processors.Type: ApplicationFiled: November 21, 2011Publication date: December 13, 2012Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventor: Teng-Chang CHANG
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Publication number: 20110119454Abstract: A display system for simultaneous displaying of windows generated by a plurality of window systems belonging to the same desktop or laptop platform includes a master computer device with its display device and at least one slave computer device, a shared memory, an input means and an output means, as described herein. Each of the master computer device and the at least one slave computer device has a corresponding window system. The shared memory is coupled to the computer devices and is accessible by the master computer device and the at least one slave computer device. The input means receives multiple windows simultaneously generated by the window systems of the master computer device and the at least one slave computer device. The output means generates the multiple windows for the display device of the master computer device. In support of these operations, the master computer device and the at least one slave computer device simultaneously read and write window data stored in the shared memory.Type: ApplicationFiled: November 17, 2009Publication date: May 19, 2011Inventors: Hsiang-Tsung KUNG, Teng-Chang CHANG, Shao-Hsuan KAO
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Publication number: 20110113426Abstract: An apparatus for managing a running virtual machine on a desktop or laptop platform includes a first computer device, a second computer device and a shared memory. The first computer device has a first switching hypervisor on which a virtual machine runs. The second computer device has a second switching hypervisor, wherein the second switching hypervisor is in communication with the first switching hypervisor. The shared memory is coupled to the first and second computer devices, and is accessible by the first and second switching hypervisors, wherein the first switching hypervisor stores status information of the virtual machine into the shared memory.Type: ApplicationFiled: November 9, 2009Publication date: May 12, 2011Inventors: Hsiang-Tsung KUNG, Teng-Chang Chang, Kuang-Ming Wang
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Publication number: 20100306501Abstract: A hybrid computer system is provided, including first and second computer devices. The first computer device is configured with the second computer device via a connection unit. Each of the first computer device and the second computer device is capable of operating independently when the first computer device and the second computer device are separated. The first computer device and the second computer device communicate with each other in a master-slave structure and combined with each other into a single system. The peripheral devices of the first and second computer devices are shared, wherein the first and second computer devices are master/slave systems or slave/master systems.Type: ApplicationFiled: December 16, 2009Publication date: December 2, 2010Applicant: Institute for Information IndustryInventors: Teng-Chang Chang, Yun-Kai Hsu, Yu-Zhi Chen