Patents by Inventor Teng Chiang Lin

Teng Chiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Debug interface for multiple CPU cores
    Patent number: 9404970
    Abstract: A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of several types of packets such as a Second Access Bus (SAB) packet and Debug Access Bus (DAB) packet. The cores include specified resources and non-specified resources. A core that executes a transaction in response to a SAB packet accesses a non-specified resource and a core that executes a transaction in response to a DAB packet accesses a specified resources. A debug specification identifies the specified resources as being accessible by a debug controller. The debug specification does not identify the non-specified resources as being accessible by the debug controller.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: August 2, 2016
    Assignee: CAVIUM, INC.
    Inventors: Teng Chiang Lin, Gerald Lampert, Nitin Prakash, Andy Wang, Bryan W. Chin
  • DEBUG INTERFACE FOR MULTIPLE CPU CORES
    Publication number: 20160139201
    Abstract: A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of several types of packets such as a Second Access Bus (SAB) packet and Debug Access Bus (DAB) packet. The cores include specified resources and non-specified resources. A core that executes a transaction in response to a SAB packet accesses a non-specified resource and a core that executes a transaction in response to a DAB packet accesses a specified resources. A debug specification identifies the specified resources as being accessible by a debug controller. The debug specification does not identify the non-specified resources as being accessible by the debug controller.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 19, 2016
    Inventors: Teng Chiang Lin, Gerald Lampert, Nitin Prakash, Andy Wang, Bryan W. Chin
  • SHARED PIPELINE ARCHITECTURE FOR MOTION VECTOR PREDICTION AND RESIDUAL DECODING
    Publication number: 20090003451
    Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
    Type: Application
    Filed: August 20, 2008
    Publication date: January 1, 2009
    Applicant: MICRONAS USA, INC.
    Inventors: Teng Chiang Lin, Weimin Zeng
  • Shared pipeline architecture for motion vector prediction and residual decoding
    Patent number: 7430238
    Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: September 30, 2008
    Assignee: Micronas USA, Inc.
    Inventors: Teng Chiang Lin, Weimin Zeng