Patents by Inventor Teng-Chin Kuo
Teng-Chin Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9494873Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.Type: GrantFiled: August 28, 2014Date of Patent: November 15, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: En-Chiuan Liou, Teng-Chin Kuo, Yuan-Chi Pai, Chun-Chi Yu
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Patent number: 9482964Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.Type: GrantFiled: May 15, 2014Date of Patent: November 1, 2016Assignee: United Microelectronics CorpInventors: En-Chiuan Liou, Chia-Chang Hsu, Yi-Ting Chen, Teng-Chin Kuo, Chun-Chi Yu
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Patent number: 9448471Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.Type: GrantFiled: July 21, 2014Date of Patent: September 20, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Yu-Cheng Tung, Teng-Chin Kuo, Yuan-Chi Pai, Chun-Chi Yu
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Patent number: 9400435Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.Type: GrantFiled: August 12, 2014Date of Patent: July 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chia-Chang Hsu, Teng-Chin Kuo, Chia-Hung Wang, Tuan-Yen Yu, Yuan-Chi Pai, Chun-Chi Yu
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Publication number: 20160172308Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.Type: ApplicationFiled: February 24, 2016Publication date: June 16, 2016Inventors: En-Chiuan Liou, Teng-Chin Kuo, Yi-Ting Chen
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Publication number: 20160126194Abstract: The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first direction, and an outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped.Type: ApplicationFiled: November 5, 2014Publication date: May 5, 2016Inventors: Chia-Chang Hsu, Teng-Chin Kuo, En-Chiuan Liou
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Publication number: 20160103396Abstract: A double patterning method comprises the following steps. First of all, a target layer and a mask layer stacked thereon are provided. Next, a first pattern opening is formed in the mask layer, and a width of the first pattern opening is measured to obtain a measuring value. Then, a second pattern opening is formed in the mask layer based on the measuring value, wherein the second pattern opening and the first pattern opening are co-planar. Finally, a bias trimming process is performed to trim the first pattern opening and the second pattern opening.Type: ApplicationFiled: October 13, 2014Publication date: April 14, 2016Inventors: En-Chiuan Liou, Teng-Chin Kuo, Chun-Chi Yu
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Patent number: 9305884Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.Type: GrantFiled: September 26, 2014Date of Patent: April 5, 2016Assignee: United Microelectronics Corp.Inventors: En-Chiuan Liou, Teng-Chin Kuo, Yi-Ting Chen
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Publication number: 20160093573Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: En-Chiuan Liou, Teng-Chin Kuo, Yi-Ting Chen
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Publication number: 20160018741Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.Type: ApplicationFiled: August 28, 2014Publication date: January 21, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: EN-CHIUAN LIOU, TENG-CHIN KUO, YUAN-CHI PAI, CHUN-CHI YU
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Publication number: 20160018728Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.Type: ApplicationFiled: July 21, 2014Publication date: January 21, 2016Inventors: En-Chiuan Liou, Yu-Cheng Tung, Teng-Chin Kuo, Yuan-Chi Pai, Chun-Chi Yu
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Publication number: 20150362905Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.Type: ApplicationFiled: August 12, 2014Publication date: December 17, 2015Inventors: En-Chiuan Liou, Chia-Chang Hsu, Teng-Chin Kuo, Chia-Hung Wang, Tuan-Yen Yu, Yuan-Chi Pai, Chun-Chi Yu
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Publication number: 20150293461Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.Type: ApplicationFiled: May 15, 2014Publication date: October 15, 2015Applicant: United Microelectronics Corp.Inventors: En-Chiuan Liou, Chia-Chang Hsu, Yi-Ting Chen, Teng-Chin Kuo, Chun-Chi Yu