Abstract: Methods for selecting integrated circuit dies based on pre-determined criteria are disclosed. A disclosed method includes binning tools that characterizes multiple integrated circuit dies based on performance attributes. Each integrated circuit die is labeled with an identifier that represents bin location of the integrated circuit die within a die storage structure. A user can search for integrated circuit dies that matches certain performance grading by providing a performance description to an input interface on testing equipment. A tester is then configured to perform a screening to identify the physical locations of integrated circuit dies that match the retrieved identifiers from the die storage structure.

Abstract: An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that generates the control signal to program the shift register.

Abstract: A circuit includes a phase detector circuit, a shift register ring circuit, and a phase shift circuit. The phase detector circuit generates an indication of a phase error between a periodic signal and an input signal. The shift register ring circuit shifts stored signals through a variable number of storage circuits coupled in the shift register ring circuit. The variable number of storage circuits coupled in the shift register ring circuit is determined based on the indication of the phase error. The phase shift circuit adjusts a phase of the periodic signal based on the stored signals.

Abstract: An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that generates the control signal to program the shift register.

Abstract: A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.

Abstract: A clock data recovery circuit includes a phase detector circuit, a filter circuit, a parts per million (PPM) detector circuit, a PPM decoder circuit, a summation circuit, and a phase interpolator circuit. The phase detector circuit generates a phase error signal based on a periodic signal and a data signal. The filter circuit generates a filtered signal based on the phase error signal. The PPM detector circuit and the PPM decoder circuit generate control signals based on the filtered signal. The phase interpolator circuit generates the periodic signal. The clock data recovery circuit adjusts a phase of the periodic signal based on the filtered signal and the control signals in response to variations in a data rate of the data signal using spread-spectrum clocking in order to track changes in the data rate of the data signal.

Abstract: A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value.

Abstract: An integrated circuit configured to selectively provide power to used portions of a memory array is presented. The integrated circuit includes an array of memory cells for storing digital data and a power bus interconnecting structure. The power bus interconnecting structure includes global power buses in communication with local power buses through programmable vias. The array of memory cells are remapped so that unused column portions of the memory array become unused row portions of the memory array. The programmable vias are selectively located during design of the integrated circuit, providing power to the used portions of the memory array.

Abstract: Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.