Patents by Inventor Teng-Chun Hsu

Teng-Chun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230259306
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: performing a first write operation based on a first programming mode to sequentially write first data to a plurality of first chip enabled regions via a plurality of channels; after the first write operation is performed, performing a second write operation based on a second programming mode to sequentially write second data to the first chip enabled regions and at least one second chip enabled region via the channels. A total number of the first chip enabled regions is larger than a total number of the second chip enabled region.
    Type: Application
    Filed: March 14, 2022
    Publication date: August 17, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Teng-Chun Hsu, Chang Han Hsieh
  • Patent number: 9424177
    Abstract: A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 23, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Po-Ting Chen, Shih-Kung Lin, Teng-Chun Hsu
  • Patent number: 9312011
    Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first logical unit and at least one second logical unit, and the data includes first data and second data; storing first data into at least one first physical erasing unit and filling the first physical erasing unit with the first data; storing second data into at least one second physical erasing unit; determining whether a remaining space of each second physical erasing unit is less than a threshold; if the remaining space of one of the at least one second physical erasing unit is less than the threshold, selecting at least one fourth physical erasing unit from a spare area and writing the second data into the at least one second physical erasing unit and the at least one fourth physical erasing unit.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: April 12, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Hong-Lipp Ko, Kheng-Joo Tan, Teng-Chun Hsu, Chia-Hung Chien
  • Publication number: 20160099062
    Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first logical unit and at least one second logical unit, and the data includes first data and second data; storing first data into at least one first physical erasing unit and filling the first physical erasing unit with the first data; storing second data into at least one second physical erasing unit; determining whether a remaining space of each second physical erasing unit is less than a threshold; if the remaining space of one of the at least one second physical erasing unit is less than the threshold, selecting at least one fourth physical erasing unit from a spare area and writing the second data into the at least one second physical erasing unit and the at least one fourth physical erasing unit.
    Type: Application
    Filed: December 1, 2014
    Publication date: April 7, 2016
    Inventors: Hong-Lipp Ko, Kheng-Joo Tan, Teng-Chun Hsu, Chia-Hung Chien
  • Patent number: 9146861
    Abstract: A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: September 29, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Hong-Lipp Ko, Teng-Chun Hsu, Po-Ting Chen, Te-Chang Tsui
  • Publication number: 20150046632
    Abstract: A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded.
    Type: Application
    Filed: October 16, 2013
    Publication date: February 12, 2015
    Applicant: Phison Electronics Corp.
    Inventors: Hong-Lipp Ko, Teng-Chun Hsu, Po-Ting Chen, Te-Chang Tsui
  • Patent number: 8902671
    Abstract: A method for programming data is provided for a memory storage device having a rewritable non-volatile memory module and a buffer memory. The method includes receiving a plurality of data including a first-type data and at least one second-type data, and a size of the first-type data is smaller than a data size threshold. The method includes temporarily storing the plurality of data into the buffer memory, and programming the first-type data and at least one part of the at least one second-type data stored in the buffer memory into a physical program unit set if it is determined that the plurality of data are complied with a predetermined condition. The method includes obtaining writing statuses of the first-type data and the at least one part of the at least one second-type data at the same time.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: December 2, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Hong-Lipp Ko, Kuo-Lung Lee, Teng-Chun Hsu
  • Publication number: 20140215130
    Abstract: A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state.
    Type: Application
    Filed: March 14, 2013
    Publication date: July 31, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Po-Ting Chen, Shih-Kung Lin, Teng-Chun Hsu
  • Publication number: 20140140142
    Abstract: A method for programming data is provided for a memory storage device having a rewritable non-volatile memory module and a buffer memory. The method includes receiving a plurality of data including a first-type data and at least one second-type data, and a size of the first-type data is smaller than a data size threshold. The method includes temporarily storing the plurality of data into the buffer memory, and programming the first-type data and at least one part of the at least one second-type data stored in the buffer memory into a physical program unit set if it is determined that the plurality of data are complied with a predetermined condition. The method includes obtaining writing statuses of the first-type data and the at least one part of the at least one second-type data at the same time.
    Type: Application
    Filed: March 6, 2013
    Publication date: May 22, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Hong-Lipp Ko, Kuo-Lung Lee, Teng-Chun Hsu