Abstract: A one-time programmable nonvolatile memory cell includes a substrate providing a first conductivity type well and a second conductivity type well, a first MOS transistor having a floating gate and a gate oxide, and an auxiliary gate and a gate oxide formed by extending one end of the floating gate and the gate oxide of the first MOS transistor from an edge of the first active region, along a second direction perpendicular to the first direction, passing through the isolation region until to cover a part or an entire of the second active region. The first and the second active regions are separated by an isolation region, and the first and second active regions and the isolation region are arranged parallel to each other along a first direction. The memory cell has an improved structure and optimized performance and a reduced size.

Abstract: A one time programmable memory having a memory cell formed on a substrate is provided. The memory cell has a transistor and an anti-fuse structure. The anti-fuse structure is consisted of a doping region, and a dielectric layer and a conductive layer is formed in the top edge corner region of an isolation structure. The upper surface of the isolation structure is lower than the surface of the substrate so as to expose the top edge corner region. The conductive layer is formed on the isolation structure and covers the top edge corner region. The dielectric layer is formed on the top edge corner region and between the doping region and the conductive layer. The memory cell stores the digital data depending on whether the dielectric layer breaks down or not.

Abstract: A method for manufacturing a MOS device with improved well control stability. The method includes the steps of providing a semiconductor substrate; forming a gate electrode according to a critical dimension on the semiconductor substrate, wherein the gate electrode comprises a gate oxide layer and a conducting gate; inspecting a real dimension of the conducting gate; determining a thickness of subsequently formed conducting gate spacers according to the real dimension of the conducting gate, such that variations of electric characteristics of the device affected by the critical dimension of the conducting gate are reduced; and forming the conducting gate spacers with the determined thickness on sidewalls of the gate electrode.

Abstract: A novel process for isolating devices on a semiconductor substrate is disclosed. An isolation layer is first formed over the semiconductor substrate and patterned into at least two isolation mesas on the substrate. Next, a blanket semiconductor layer is formed over the substrate with a thickness sufficient to cover the isolation mesas. The semiconductor layer is subjected to planarization until the isolation mesas are exposed, thus resulting in a semiconductor region between the two isolation mesas to serve as an active region for semiconductor devices.