Patents by Inventor Teng Soong PHUA

Teng Soong PHUA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9666688
    Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: May 30, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Yisuo Li, Aashit Ramachandra Kamath, Zhixian Chen, Teng Soong Phua, Xinpeng Wang, Patrick Guo-Qiang Lo
  • Publication number: 20160380080
    Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Inventors: Fujio MASUOKA, Nozomu HARADA, Hiroki NAKAMURA, Yisuo LI, Aashit Ramachandra KAMATH, Zhixian CHEN, Teng Soong PHUA, Xinpeng WANG, Patrick Guo-Qiang LO
  • Patent number: 9490362
    Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 8, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Yisuo Li, Aashit Ramachandra Kamath, Zhixian Chen, Teng Soong Phua, Xinpeng Wang, Patrick Guo-Qiang Lo
  • Publication number: 20150287822
    Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 8, 2015
    Inventors: Fujio MASUOKA, Nozomu HARADA, Hiroki NAKAMURA, Yisuo LI, Aashit Ramachandra KAMATH, Zhixian CHEN, Teng Soong PHUA, Xinpeng WANG, Patrick Guo-Qiang LO