Abstract: An in-situ evaluation method and system for loess collapsibility based on non-destructive time-domain reflection technology, includes: calculating loess dry density and mass water content; considering loess dry density, mass water content and basic physical property indicators, and evaluating loess collapsibility in situ through mathematical models. The loess collapsibility in-situ evaluation method based on the non-destructive time domain reflectometry technology of the present invention can not only realize whether the loess has collapsibility, but also has the potential to distinguish strong, medium and slight collapsibility.

Abstract: A multi-nozzle concurrent printing system includes a plurality of extrusion type nozzle assemblies, a three-axial translation mechanism and an objective table. Each nozzle assembly is provided with a nozzle, a storage barrel and a temperature control module; the three-axial translation mechanism includes an X-axial translation unit, a Y-axial translation unit and a Z-axial translation unit, and the nozzle assemblies are mounted on the Z-axial translation unit; and there are a plurality of nozzle assemblies, the printing system is provided with a concurrent calibration sensor, and the concurrent calibration sensor is taken as an original point of a coordinate system of the printing system. The printing system is provided with the plurality of nozzle assemblies which can work cooperatively or sequentially, the printing mode is flexible and changeable, and non-uniform mixing system forming of materials can be realized; and stable output of the materials in a formal printing task is guaranteed.

Abstract: A non-invasive time domain reflection probe calibration method includes: using different volume ratio of ethanol and deionized water mixed solution to calculate a test target's medium weight coefficient and waveguide length of the non-invasive time domain reflection probes; using different concentrations of NaCl solutions to calibrate a waveguide geometric dimensioning of the non-invasive time domain reflection probes; preparing compacted soil samples with known different moisture contents and densities, and calibrating a correlation parameter of compacted soil samples' dielectric constant and conductivity with moisture content and density. The method not only determines the sensitivity of the test target medium of the non-invasive time domain reflection probes, but also obtains the waveguide length and geometric dimensioning of the probe, and realizes an accurate test of moisture content and density of the soil.

Abstract: An in-situ evaluation method and system for loess collapsibility based on non-destructive time-domain reflection technology, includes: calculating loess dry density and mass water content; considering loess dry density, mass water content and basic physical property indicators, and evaluating loess collapsibility in situ through mathematical models. The loess collapsibility in-situ evaluation method based on the non-destructive time domain reflectometry technology of the present invention can not only realize whether the loess has collapsibility, but also has the potential to distinguish strong, medium and slight collapsibility.

Abstract: A monitoring technique for a melting process including monitoring a melt pool produced by a heat source during the melting process, the monitoring comprising measuring ultrasonic time of flight of the melt pool via one or more ultrasonic transducers, wherein the melt pool comprises one or more metals, alloys, or a combination thereof. A system for carrying out the monitoring technique, and melting processes and systems utilizing the monitoring technique are also provided.

Abstract: A multi-nozzle concurrent printing system includes a plurality of extrusion type nozzle assemblies, a three-axial translation mechanism and an objective table. Each nozzle assembly is provided with a nozzle, a storage barrel and a temperature control module; the three-axial translation mechanism includes an X-axial translation unit, a Y-axial translation unit and a Z-axial translation unit, and the nozzle assemblies are mounted on the Z-axial translation unit; and there are a plurality of nozzle assemblies, the printing system is provided with a concurrent calibration sensor, and the concurrent calibration sensor is taken as an original point of a coordinate system of the printing system. The printing system is provided with the plurality of nozzle assemblies which can work cooperatively or sequentially, the printing mode is flexible and changeable, and non-uniform mixing system forming of materials can be realized; and stable output of the materials in a formal printing task is guaranteed.

Abstract: An anti-collapse grouting consolidation system including: a grouting pump; an outer flat drill rod; a drill rig that clamps the outer flat drill rod; a sealing device, sheathed on the outer flat drill rod at the orifice of a drill hole, ensuring the outer flat drill rod is sealed with the orifice of the drill hole; and a jet grouting drill bit with bi-directional rib wings. The grouting pump jets slurry into the drill hole in a static osmotic manner through the jet grouting drill bit. A method of using an anti-collapse grouting consolidation system includes, among other things, injecting quick-setting slurry; sealing an orifice hole of the drill hole by an orifice sealing device; and keeping an anti-collapse jet grouting drill bit with bi-directional rib wings repeatedly moving up and down and rotating at a repair segment to repair the repair segment.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: An anti-collapse jet grouting drill bit with bi-directional rib wings, and a grouting consolidation including: a grouting pump connected to a high-pressure pipeline, which connects to an underground drill rig; an outer flat drill rod, connected with the underground drill rig; a sealing device, sheathed on the outer flat drill rod at the orifice of a drill hole, ensuring the outer flat drill rod is sealed with the orifice of the drill hole which connects to a jet grouting drill bit with bi-directional rib wings. The grouting pump jets slurry into the drill hole in a static osmotic manner through the jet rib wing drill bit, while the underground jet drill rig is rotated by the force of outer flat drill rod. The rotation of the jet slurry and the rib wings, repairs the hole wall by cutting chippings or squeezing the chippings back into the hole wall.

Abstract: A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.

Abstract: Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.

Abstract: Circuits and methods for performing harmonic rejection mixing are provided. In some embodiments, the circuit comprises: a first amplifier that amplifies a received signal at a first gain; a second amplifier that amplifies the received signal at a fraction of the first gain; a mixer that receives a local oscillator signal having a first fundamental frequency and the first amplifier output, and outputs a first mixed signal; a second mixer that receives a second local oscillator signal having a fundamental frequency that is a multiple of the first fundamental frequency and the second amplifier output, and outputs a second mixed signal; and an output stage that receives the first and second mixed signals and outputs a sum of the first and second mixed signals.

Abstract: Circuits for temperature monitoring are provided having a first voltage output and a second voltage output comprising: a first transistor having a first transistor input, a first transistor output, and a first transistor control, wherein the first transistor input is connected to a supply voltage; a first diode having a first diode input and a first diode output, wherein the first diode output is connected to ground and the first diode input is connected to the first transistor output, the first transistor control and the first voltage output; a second transistor having a second transistor input, a second transistor output, and a second transistor control, wherein the second transistor input is connected to a supply voltage; a second diode having a second diode input and a second diode output, wherein the second diode input is connected to the second transistor output, the second transistor control, and the second voltage output.

Abstract: Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.

Abstract: Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.