Abstract: Examples of the present application disclose a memory controller, a memory system and an operation method thereof. The operation method includes: determining that a memory device is in a first use state in response to determining that a read error is occurred in the memory device of the memory system; determining a first voltage offset corresponding to the first use state according to a preset mapping relationship that includes a corresponding relationship between a use state of the memory device and a voltage offset, the voltage offset including an offset value relative to a preset reference read voltage; and obtaining at least one first read voltage for performing a read operation on the memory device in the first use state according to the preset reference read voltage and the first voltage offset.

Abstract: Examples provide for error correction. The error correction includes: obtaining first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and performing first soft decision decoding according to the first soft data and the first hard read data, or according to the first soft data and the second hard read data, wherein the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.

Abstract: A memory system, an operation method thereof and a readable storage medium are provided according to examples of this disclosure. The memory system including: a memory device including a plurality of memory blocks, each of which including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; a memory controller coupled to the memory device and configured to: acquire a read retry voltage with both a first-type read retry table and a second-type read retry table; control the memory device to perform a read retry operation with the read retry voltage.

Abstract: Examples provide for error correction. The error correction includes: obtaining first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and performing first soft decision decoding according to the first soft data and the first hard read data, or according to the first soft data and the second hard read data, wherein the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.

Abstract: A memory system and operation method thereof are provided according to implementations of this disclosure. The memory system comprises: at least one memory device and a memory controller coupled to the at least one memory device. The memory controller is configured to: perform part or all of a read error processing flow for at least two times, in response to a failure of a first read operation when performing a read operation on a memory region in the memory device.

Abstract: In examples, a method of controlling a memory system comprises obtaining a first soft-bit data corresponding to a hard-bit data read from a memory and a first lookup table, where the first lookup table comprises a first log-likelihood ratio determined based on a first reference read voltage of the memory. The method comprises performing a first soft decoding operation according to the first log-likelihood ratio and the first soft-bit data. The method comprises performing at least one shift to the first log-likelihood ratio and performing a second soft decoding operation according to a log-likelihood ratio after each shift and the first soft-bit data when the first soft decoding operation is determined to have failed to decode.