Abstract: A method for isolating at least one conductive via from a surrounding glass substrate is provided. A support layer is formed over at least one surface of the glass substrate. Thereafter, the glass substrate is removed. As a result, the at least one conductive via can be analyzed without interference from the glass substrate.

Abstract: A method for isolating at least one conductive via from a surrounding glass substrate is provided. A support layer is formed over at least one surface of the glass substrate. Thereafter, the glass substrate is removed. As a result, the at least one conductive via can be analyzed without interference from the glass substrate.

Abstract: The present disclosure relates to a method and an apparatus for generating a three-dimensional model, a device, and a storage medium. The method includes: a scanned texture image and a depth image corresponding to the texture image are acquired; the texture image is processed by a pre-trained mask region convolutional neural network to determine at least one region of interest on the texture image and category information and mask information of each of the at least one region of interest; the depth image is updated according to the category information and the mask information of each of the at least one region of interest to obtain a updated depth image; and a three-dimensional model corresponding to the updated depth image is constructed.

Abstract: Embodiments of the present disclosure include devices, and methods of making such devices, for delivery of one or more active agents with short or long zero-order release kinetics. Embodiments also include implantable or injectable drug delivery systems capable of controlled release over long periods of time for therapeutic agents.

Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.

Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.

Abstract: Embodiments of the present disclosure include devices, and methods of making such devices, for delivery of one or more active agents with short or long zero-order release kinetics. Embodiments also include implantable or injectable drug delivery systems capable of controlled release over long periods of time for therapeutic agents.

Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.

Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.