Abstract: Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.

Abstract: Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.

Abstract: A method to perform a hybrid Register Transfer Level (RTL)/gate-level (GL) fault injection simulation of a hardware design comprises generating a list of one or more fault nodes in a GL netlist for the hardware design, mapping functionally equivalent comparison points between RTL logic for the hardware design and GL netlist of the hardware design, identifying a nearest set of downstream comparison points for one or more logic paths for the one or more fault nodes, identifying a nearest set of upstream comparison points for the one or more identified downstream comparison points, replacing RTL logic with equivalent GL netlist logic to provide hybrid RTL/GL netlist in code, and performing fault injection simulating using the hybrid RTL/GL netlist code

Abstract: An embodiment of a method and device for detecting a signal and generating bit soft-output of a multiple-input multiple-output system is provided. The device includes at least one channel estimates pre-processing unit, one received vector processing and one detection and soft-output generation unit. The pre-processing unit calculates multiple QR Decompositions of the input channel estimation matrix. The detection and soft-output generation unit computes near optimal bit soft output information with a deterministic complexity and latency. It may implement a reduced complexity search method. Globally, embodiments of the invention may allow achieving low complexity, high data rate, scalability in terms of the dimension of the MIMO system and flexibility versus the supported modulation order, all potentially key factors for most MIMO wireless transmission applications.

Abstract: An embodiment of a method and device for detecting a signal and generating bit soft-output of a multiple-input multiple-output system is provided. The device includes at least one channel estimates pre-processing unit, one received vector processing and one detection and soft-output generation unit. The pre-processing unit calculates multiple QR Decompositions of the input channel estimation matrix. The detection and soft-output generation unit computes near optimal bit soft output information with a deterministic complexity and latency. It may implement a reduced complexity search method. Globally, embodiments of the invention may allow achieving low complexity, high data rate, scalability in terms of the dimension of the MIMO system and flexibility versus the supported modulation order, all potentially key factors for most MIMO wireless transmission applications.