Abstract: A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

Abstract: A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.