Abstract: A composition includes an electrode made of Lithium Manganese Oxyfluoride (LMOF). A single layer separator adheres to a surface of the electrode, is a dielectric that is conductive for Lithium ions but not electrons, and has top and bottom sides. A solid polymer electrolyte (SPE) saturates the electrode so that the LMOF is between 55 percent and 85 percent by mass of a composition of the LMOF electrode and the SPE is between 7.5 percent and 20 percent by mass of the composition of the LMOF electrode. The SPE saturates the separator so that the SPE resides both on the separator top and bottom sides so that the SPE residing on the separator top side contacts the surface. The LMOF exhibits X-Ray Diffraction spectrum peaks between twenty-two and twenty-four 2-theta degrees, between forty-eight and fifty 2-theta degrees, between fifty-four and fifty-six 2-theta degrees, and between fifty-six and fifty-eight 2-theta degrees.

Abstract: An interconnect structure including conducting layers of topological semi-metals and/or topological insulators. To increase charge carrier density in the conducting layers, a charge carrier doping layer present on at least one surface of the one or more conductive layers of topological semi-metals. The charge carrying doping layers have a charge carrier density greater than the topological semi-metals and/or topological insulators of the one or more conductive layers.

Abstract: A silicon-based electrode forms an interface with a layer pair being: 1. a thin, semi-dielectric layer made of a lithium (Li) compound, e.g. lithium fluoride, LiF, disposed on and adheres to the electrode surface of the silicon-based electrode and 2. an molten-ion conductive layer of a lithium containing salt (lithium salt layer) disposed on the semi-dielectric layer. One or more device layers can be disposed on the layer pair to make devices such as energy storage devices, like batteries. The interface has a low resistivity that reduces the energy losses and generated heat of the devices.

Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.

Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.

Abstract: A method of fabricating a neuromorphic device includes forming a variable-resistance layer between a first terminal and a second terminal, the variable-resistance layer varies in resistance based on an oxygen concentration in the variable-resistance layer. The method further includes forming an electrolyte layer over the variable-resistance layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. The method further includes forming a gate layer over the electrolyte layer to apply a voltage on the electrolyte layer and the variable-resistance layer, the gate layer formed using an oxygen scavenging material.

Abstract: A silicon-based electrode forms an interface with a layer pair being: 1. a thin, semi-dielectric layer made of a lithium (Li) compound, e.g. lithium fluoride, LiF, disposed on and adheres to the electrode surface of the silicon-based electrode and 2. an molten-ion conductive layer of a lithium containing salt (lithium salt layer) disposed on the semi-dielectric layer. One or more device layers can be disposed on the layer pair to make devices such as energy storage devices, like batteries. The interface has a low resistivity that reduces the energy losses and generated heat of the devices.

Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.

Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.

Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.

Abstract: A neuromorphic device includes a metal-oxide channel layer that has a variable-resistance between a first terminal and a second terminal. The neuromorphic device further includes a metal-oxide charge transfer layer over the metal-oxide channel layer that causes the metal-oxide channel layer to vary in resistance based on charge exchange between the metal-oxide charge transfer layer and the metal-oxide channel layer in accordance with an applied input signal. The neuromorphic device further includes a third terminal that applies the signal to the metal-oxide charge transfer layer and the metal-oxide channel layer.

Abstract: A neuromorphic device includes a metal-oxide channel layer that has a variable-resistance between a first terminal and a second terminal. The neuromorphic device further includes a metal-oxide charge transfer layer over the metal-oxide channel layer that causes the metal-oxide channel layer to vary in resistance based on charge exchange between the metal-oxide charge transfer layer and the metal-oxide channel layer in accordance with an applied input signal. The neuromorphic device further includes a third terminal that applies the signal to the metal-oxide charge transfer layer and the metal-oxide channel layer.

Abstract: According to an embodiment of the present invention there is a cathode of an energy storage device. The cathode is made of Lithium Manganese Oxyfluoride (LMOF), with the approximate stoichiometry of Li2MnO2F. In some embodiments, the cathode is made of Lithium Manganese Oxyfluoride (LMOF), Li2MnO2F combined with a solid polymer electrolyte (SPE). Other materials such as conductive material and binders can be included in the cathode. Methods of making are disclosed. According to an embodiment of the present invention there is a composition of matter. The composition is made of Lithium Manganese Oxyfluoride (LMOF), with the approximate stoichiometry of Li2MnO2F combined with a solid polymer electrolyte (SPE). Other materials such as conductive material and binders can be included in the cathode. Methods of making are disclosed. The composition can be used as a cathode in an energy storage device. An energy storage device, e.g. a battery, is disclosed.

Abstract: A method of fabricating a neuromorphic device includes forming a variable-resistance layer between a first terminal and a second terminal, the variable-resistance layer varies in resistance based on an oxygen concentration in the variable-resistance layer. The method further includes forming an electrolyte layer over the variable-resistance layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. The method further includes forming a gate layer over the electrolyte layer to apply a voltage on the electrolyte layer and the variable-resistance layer, the gate layer formed using an oxygen scavenging material.

Abstract: Making a rechargeable Lithium energy storage device begins by forming one or more trenches in a solid silicon substrate. One or more region interface precursors are deposited in the trench followed by one or more anode materials, one or more solid polymer electrolytes (SPE), and one or more cathode materials. Electrically cycling transforms the battery structures prior to full operation of the battery. Some, or all, of the process steps can be performed while the materials are within the trench, i.e. in-situ.

Abstract: Techniques for fabrication of kesterite Cu—Zn—Sn—(Se,S) films and improved photovoltaic devices based on these films are provided. In one aspect, a method of fabricating a kesterite film having a formula Cu2?xZn1+ySn(S1?zSez)4+q, wherein 0?x?1; 0?y?1; 0?z?1; and ?1?q?1 is provided. The method includes the following steps. A substrate is provided. A bulk precursor layer is formed on the substrate, the bulk precursor layer comprising Cu, Zn, Sn and at least one of S and Se. A capping layer is formed on the bulk precursor layer, the capping layer comprising at least one of Sn, S and Se. The bulk precursor layer and the capping layer are annealed under conditions sufficient to produce the kesterite film having values of x, y, z and q for any given part of the film that deviate from average values of x, y, z and q throughout the film by less than 20 percent.

Abstract: Techniques for fabrication of kesterite Cu—Zn—Sn—(Se,S) films and improved photovoltaic devices based on these films are provided. In one aspect, a method of fabricating a kesterite film having a formula Cu2?xZn1+ySn(S1?zSez)4+q, wherein 0?x?1; 0?y?1; 0?z?1; and ?1?q?1 is provided. The method includes the following steps. A substrate is provided. A bulk precursor layer is formed on the substrate, the bulk precursor layer comprising Cu, Zn, Sn and at least one of S and Se. A capping layer is formed on the bulk precursor layer, the capping layer comprising at least one of Sn, S and Se. The bulk precursor layer and the capping layer are annealed under conditions sufficient to produce the kesterite film having values of x, y, z and q for any given part of the film that deviate from average values of x, y, z and q throughout the film by less than 20 percent.

Abstract: Techniques for fabrication of kesterite Cu—Zn—Sn—(Se,S) films and improved photovoltaic devices based on these films are provided. In one aspect, a method of fabricating a kesterite film having a formula Cu2?xZn1+ySn(S1?zSez)4+q, wherein 0?x?1; 0?y?1; 0?z?1; and ?1?q?1 is provided. The method includes the following steps. A substrate is provided. A bulk precursor layer is formed on the substrate, the bulk precursor layer comprising Cu, Zn, Sn and at least one of S and Se. A capping layer is formed on the bulk precursor layer, the capping layer comprising at least one of Sn, S and Se. The bulk precursor layer and the capping layer are annealed under conditions sufficient to produce the kesterite film having values of x, y, z and q for any given part of the film that deviate from average values of x, y, z and q throughout the film by less than 20 percent.

Abstract: Low-temperature sulfurization/selenization heat treatment processes for photovoltaic devices are provided. In one aspect, a method for fabricating a photovoltaic device is provided. The method includes the following steps. A substrate is provided that is either (i) formed from an electrically conductive material or (ii) coated with at least one layer of a conductive material. A chalcogenide absorber layer is formed on the substrate. A buffer layer is formed on the absorber layer. A transparent front contact is formed on the buffer layer. The device is contacted with a chalcogen-containing vapor having a sulfur and/or selenium compound under conditions sufficient to improve device performance by filling chalcogen vacancies within the absorber layer or the buffer layer or by passivating one or more of grain boundaries in the absorber layer, an interface between the absorber layer and the buffer layer and an interface between the absorber layer and the substrate.

Abstract: Low-temperature sulfurization/selenization heat treatment processes for photovoltaic devices are provided. In one aspect, a method for fabricating a photovoltaic device is provided. The method includes the following steps. A substrate is provided that is either (i) formed from an electrically conductive material or (ii) coated with at least one layer of a conductive material. A chalcogenide absorber layer is formed on the substrate. A buffer layer is formed on the absorber layer. A transparent front contact is formed on the buffer layer. The device is contacted with a chalcogen-containing vapor having a sulfur and/or selenium compound under conditions sufficient to improve device performance by filling chalcogen vacancies within the absorber layer or the buffer layer or by passivating one or more of grain boundaries in the absorber layer, an interface between the absorber layer and the buffer layer and an interface between the absorber layer and the substrate.