Patents by Inventor Teppei Akazawa

Teppei Akazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9330842
    Abstract: In a monolithic ceramic electronic component, given that an interval between outer-layer dummy conductors adjacent to each other in an outer layer portion is d1, and that an interval between first and second inner electrodes adjacent to each other in an inner layer portion is d2, 1.7d2?d1 is satisfied. By reducing a density of the outer-layer dummy conductors in the outer layer portion on that condition, pressing of the inner electrodes through the outer-layer dummy conductors is relieved in a pressing step before firing. As a result, a distance between the inner electrodes can be prevented from being locally shortened. It is hence possible to effectively reduce and prevent degradation of reliability of the monolithic ceramic electronic component, e.g., a reduction of BDV.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: May 3, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Sakuratani, Teppei Akazawa
  • Patent number: 8902564
    Abstract: In a multilayer ceramic electronic component, when a region of a ceramic body in layers where neither of a first internal electrode and a second internal electrode is provided as viewed in a direction in which a plurality of ceramic layers are stacked on one another is defined as a non-effective layer region, a dummy lead-through conductor is arranged in the non-effective layer region so as to lead to at least two locations on portions of superficies of the ceramic body and be electrically connected to a second external electrode. When a conductive medium is brought into contact with one of a plurality of exposed edges of the dummy lead-through conductor, a current is also applied to the other exposed edges.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 2, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Teppei Akazawa, Kenjiro Hadano, Masahiro Sakuratani
  • Publication number: 20140146438
    Abstract: In a multilayer ceramic electronic component, when a region of a ceramic body in layers where neither of a first internal electrode and a second internal electrode is provided as viewed in a direction in which a plurality of ceramic layers are stacked on one another is defined as a non-effective layer region, a dummy lead-through conductor is arranged in the non-effective layer region so as to lead to at least two locations on portions of superficies of the ceramic body and be electrically connected to a second external electrode. When a conductive medium is brought into contact with one of a plurality of exposed edges of the dummy lead-through conductor, a current is also applied to the other exposed edges.
    Type: Application
    Filed: January 29, 2014
    Publication date: May 29, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Teppei AKAZAWA, Kenjiro HADANO, Masahiro SAKURATANI
  • Publication number: 20140133063
    Abstract: In a monolithic ceramic electronic component, given that an interval between outer-layer dummy conductors adjacent to each other in an outer layer portion is d1, and that an interval between first and second inner electrodes adjacent to each other in an inner layer portion is d2, 1.7d2?d1 is satisfied. By reducing a density of the outer-layer dummy conductors in the outer layer portion on that condition, pressing of the inner electrodes through the outer-layer dummy conductors is relieved in a pressing step before firing. As a result, a distance between the inner electrodes can be prevented from being locally shortened. It is hence possible to effectively reduce and prevent degradation of reliability of the monolithic ceramic electronic component, e.g., a reduction of BDV.
    Type: Application
    Filed: December 30, 2013
    Publication date: May 15, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro SAKURATANI, Teppei AKAZAWA
  • Patent number: 8687344
    Abstract: A laminated ceramic electronic component includes curved surface portions provided in an outer surface of a ceramic element assembly, and internal conductors provided within the ceramic element assembly that are exposed in the curved surface portions and principal surfaces to define starting points for plating deposition. A base layer, in an external conductor, which is defined by a plating film is arranged so as to directly cover the exposed portions of the internal conductors.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 1, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Teppei Akazawa, Kenjiro Hadano, Masahiro Sakuratani
  • Patent number: 8675341
    Abstract: In a multilayer ceramic electronic component, when a region of a ceramic body in layers where neither of a first internal electrode and a second internal electrode is provided as viewed in a direction in which a plurality of ceramic layers are stacked on one another is defined as a non-effective layer region, a dummy lead-through conductor is arranged in the non-effective layer region so as to lead to at least two locations on portions of superficies of the ceramic body and be electrically connected to a second external electrode. When a conductive medium is brought into contact with one of a plurality of exposed edges of the dummy lead-through conductor, a current is also applied to the other exposed edges.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 18, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Teppei Akazawa, Kenjiro Hadano, Masahiro Sakuratani
  • Patent number: 8654504
    Abstract: In a monolithic ceramic electronic component, given that an interval between outer-layer dummy conductors adjacent to each other in an outer layer portion is d1, and that an interval between first and second inner electrodes adjacent to each other in an inner layer portion is d2, 1.7d2?d1 is satisfied. By reducing a density of the outer-layer dummy conductors in the outer layer portion on that condition, pressing of the inner electrodes through the outer-layer dummy conductors is relieved in a pressing step before firing. As a result, a distance between the inner electrodes can be prevented from being locally shortened. It is hence possible to effectively reduce and prevent degradation of reliability of the monolithic ceramic electronic component, e.g., a reduction of BDV.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 18, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Sakuratani, Teppei Akazawa
  • Publication number: 20130033154
    Abstract: In a monolithic ceramic electronic component, given that an interval between outer-layer dummy conductors adjacent to each other in an outer layer portion is d1, and that an interval between first and second inner electrodes adjacent to each other in an inner layer portion is d2, 1.7d2?d1 is satisfied. By reducing a density of the outer-layer dummy conductors in the outer layer portion on that condition, pressing of the inner electrodes through the outer-layer dummy conductors is relieved in a pressing step before firing. As a result, a distance between the inner electrodes can be prevented from being locally shortened. It is hence possible to effectively reduce and prevent degradation of reliability of the monolithic ceramic electronic component, e.g., a reduction of BDV.
    Type: Application
    Filed: July 30, 2012
    Publication date: February 7, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Masahiro SAKURATANI, Teppei AKAZAWA
  • Publication number: 20120320495
    Abstract: A laminated ceramic electronic component includes curved surface portions provided in an outer surface of a ceramic element assembly, and internal conductors provided within the ceramic element assembly that are exposed in the curved surface portions and principal surfaces to define starting points for plating deposition. A base layer, in an external conductor, which is defined by a plating film is arranged so as to directly cover the exposed portions of the internal conductors.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 20, 2012
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Teppei AKAZAWA, Kenjiro HADANO, Masahiro SAKURATANI
  • Publication number: 20120188684
    Abstract: In a multilayer ceramic electronic component, when a region of a ceramic body in layers where neither of a first internal electrode and a second internal electrode is provided as viewed in a direction in which a plurality of ceramic layers are stacked on one another is defined as a non-effective layer region, a dummy lead-through conductor is arranged in the non-effective layer region so as to lead to at least two locations on portions of superficies of the ceramic body and be electrically connected to a second external electrode. When a conductive medium is brought into contact with one of a plurality of exposed edges of the dummy lead-through conductor, a current is also applied to the other exposed edges.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 26, 2012
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Teppei AKAZAWA, Kenjiro HADANO, Masahiro SAKURATANI
  • Patent number: 8198972
    Abstract: An electronic component includes a coil whose inductance changes in accordance with the magnitude of a current and in which abrupt reduction in the inductance due to magnetic saturation is suppressed. A stack formed by a plurality of stacked first magnetic layers includes a coil formed by coil electrodes connected to one another in the stack. A first nonmagnetic layer is arranged in such a manner as to cut across the coil. When viewed in a stacking direction, a second nonmagnetic layer is formed in a region outside of a region in which the coil is formed. The structure of the second nonmagnetic layer on the upper side of the first nonmagnetic layer in the stacking direction is different from a structure of the second magnetic layer on the lower side of the first nonmagnetic layer in the stacking direction.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: June 12, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Teppei Akazawa
  • Publication number: 20110018673
    Abstract: An electronic component includes a coil whose inductance changes in accordance with the magnitude of a current and in which abrupt reduction in the inductance due to magnetic saturation is suppressed. A stack formed by a plurality of stacked first magnetic layers includes a coil formed by coil electrodes connected to one another in the stack. A first nonmagnetic layer is arranged in such a manner as to cut across the coil. When viewed in a stacking direction, a second nonmagnetic layer is formed in a region outside of a region in which the coil is formed. The structure of the second nonmagnetic layer on the upper side of the first nonmagnetic layer in the stacking direction is different from a structure of the second magnetic layer on the lower side of the first nonmagnetic layer in the stacking direction.
    Type: Application
    Filed: October 5, 2010
    Publication date: January 27, 2011
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Teppei AKAZAWA