Patents by Inventor Teppei Iwase
Teppei Iwase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10866509Abstract: A mold includes a rugged pattern layer, an inorganic sheet layer, and an elastic sheet layer. The inorganic sheet layer is formed of an inorganic material and supports the rugged pattern layer. The elastic sheet layer supports the inorganic sheet layer.Type: GrantFiled: June 9, 2017Date of Patent: December 15, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Akihiro Ishikawa, Tosihiko Wada, Teppei Iwase
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Patent number: 10578775Abstract: A film structural member includes a recessed portion on a transparent substrate, metal wiring on a base of the recessed portion, and a particle layer on the metal wiring. The particle layer is configured as an aggregate of particles having an average particle diameter of 300 nm or smaller.Type: GrantFiled: February 21, 2018Date of Patent: March 3, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Keitaro Fujii, Teppei Iwase, Yuji Yamamoto, Nobuyuki Kamikihara
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Publication number: 20180321584Abstract: A mold includes a rugged pattern layer, an inorganic sheet layer, and an elastic sheet layer. The inorganic sheet layer is formed of an inorganic material and supports the rugged pattern layer. The elastic sheet layer supports the inorganic sheet layer.Type: ApplicationFiled: June 9, 2017Publication date: November 8, 2018Inventors: AKIHIRO ISHIKAWA, TOSIHIKO WADA, TEPPEI IWASE
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Patent number: 10105874Abstract: An imprinting method includes a resin application process of applying a light curing resin so that the resin covers a surface of the substrate and protrudes from an outer periphery of the substrate to contact an adhesive sheet in a state where a reverse surface of the substrate is adhered to the adhesive sheet, an advance curing process of curing the light curing resin contacting the adhesive sheet by irradiating the substrate with light from the reverse surface side, a pressurizing process of pressing a fine pattern formed in a mold onto the light curing resin on the surface of the substrate, a curing process of curing the light curing resin on the surface of the substrate by irradiating the substrate with light from the surface side and a mold releasing process of releasing the mold from the light curing resin by performing peeling from a portion cured on the adhesive sheet.Type: GrantFiled: January 17, 2016Date of Patent: October 23, 2018Assignee: Panasonic Intellectial Property Management Co., Ltd.Inventors: Teppei Iwase, Akihiro Ishikawa, Toshihiko Wada
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Publication number: 20180267209Abstract: A film structural member includes a recessed portion formed on a transparent substrate, metal wiring provided on a base of the recessed portion, and a particle layer that is provided on the metal wiring and is configured as an aggregate of particles having an average particle diameter of 300 nm or smaller.Type: ApplicationFiled: February 21, 2018Publication date: September 20, 2018Inventors: KEITARO FUJII, TEPPEI IWASE, YUJI YAMAMOTO, NOBUYUKI KAMIKIHARA
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Patent number: 9950463Abstract: An imprinting device capable of realizing uniform transfer regardless of the thickness of a substrate includes a stage having a placement area for placing a substrate to which a transferred object is applied, a thin-plate mold with flexibility having a fine pattern on a first surface facing the placement area of the stage, which is held with a predetermined tension and a pressing roll which can press a second surface opposite to the first surface of the mold, in which the stage has plural adsorption holes around the placement area, and the adsorption holes start adsorption in synchronization with movement of the pressing roll.Type: GrantFiled: January 7, 2016Date of Patent: April 24, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Akihiro Ishikawa, Teppei Iwase, Toshihiko Wada
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Publication number: 20160332341Abstract: An imprinting method includes a resin application process of applying a light curing resin so that the resin covers a surface of the substrate and protrudes from an outer periphery of the substrate to contact an adhesive sheet in a state where a reverse surface of the substrate is adhered to the adhesive sheet, an advance curing process of curing the light curing resin contacting the adhesive sheet by irradiating the substrate with light from the reverse surface side, a pressurizing process of pressing a fine pattern formed in a mold onto the light curing resin on the surface of the substrate, a curing process of curing the light curing resin on the surface of the substrate by irradiating the substrate with light from the surface side and a mold releasing process of releasing the mold from the light curing resin by performing peeling from a portion cured on the adhesive sheet.Type: ApplicationFiled: January 17, 2016Publication date: November 17, 2016Inventors: TEPPEI IWASE, AKIHIRO ISHIKAWA, TOSHIHIKO WADA
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Publication number: 20160257062Abstract: An imprinting device capable of realizing uniform transfer regardless of the thickness of a substrate includes a stage having a placement area for placing a substrate to which a transferred object is applied, a thin-plate mold with flexibility having a fine pattern on a first surface facing the placement area of the stage, which is held with a predetermined tension and a pressing roll which can press a second surface opposite to the first surface of the mold, in which the stage has plural adsorption holes around the placement area, and the adsorption holes start adsorption in synchronization with movement of the pressing roll.Type: ApplicationFiled: January 7, 2016Publication date: September 8, 2016Inventors: AKIHIRO ISHIKAWA, TEPPEI IWASE, TOSHIHIKO WADA
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Publication number: 20150362634Abstract: First protrusions (321) and second protrusions (322) surrounding the first protrusions (321) are formed on the surface of an optical member (1). The first and second protrusions (321, 322) are sized for a wavelength with antireflection and have different heights or pitches.Type: ApplicationFiled: December 10, 2013Publication date: December 17, 2015Inventors: Teppei IWASE, Tosihiko WADA, Takashi TSURUTA, Yuta MORIYAMA
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Patent number: 9136219Abstract: A semiconductor device includes: a first semiconductor chip having a surface provided with first electrodes; and an expanded semiconductor chip including a second semiconductor chip and an expanded portion extending outward from at least one side surface of the second semiconductor chip. The expanded semiconductor chip has a surface provided with second electrodes. The surface of the first semiconductor chip provided with the first electrodes faces the surface of the expanded semiconductor chip provided with the second electrodes so that the first electrodes are connected to the second electrodes. Each one of the second electrodes that is connected to an associated one of the first electrodes is located only on the expanded portion.Type: GrantFiled: January 9, 2014Date of Patent: September 15, 2015Assignee: Panasonic CorporationInventors: Teppei Iwase, Kiyomi Hagihara
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Patent number: 8766418Abstract: A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.Type: GrantFiled: January 9, 2014Date of Patent: July 1, 2014Assignee: Panasonic CorporationInventors: Teppei Iwase, Takashi Yui
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Publication number: 20140124957Abstract: A semiconductor device includes: a first semiconductor chip having a surface provided with first electrodes; and an expanded semiconductor chip including a second semiconductor chip and an expanded portion extending outward from at least one side surface of the second semiconductor chip. The expanded semiconductor chip has a surface provided with second electrodes. The surface of the first semiconductor chip provided with the first electrodes faces the surface of the expanded semiconductor chip provided with the second electrodes so that the first electrodes are connected to the second electrodes. Each one of the second electrodes that is connected to an associated one of the first electrodes is located only on the expanded portion.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: PANASONIC CORPORATIONInventors: TEPPEI IWASE, KIYOMI HAGIHARA
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Publication number: 20140124911Abstract: A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: Panasonic CorporationInventors: TEPPEI IWASE, TAKASHI YUI
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Patent number: 8426965Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.Type: GrantFiled: August 6, 2012Date of Patent: April 23, 2013Assignee: Panasonic CorporationInventors: Teppei Iwase, Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa
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Publication number: 20120298310Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.Type: ApplicationFiled: August 6, 2012Publication date: November 29, 2012Inventors: Teppei IWASE, Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa
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Patent number: 8283570Abstract: A semiconductor assembly includes a multilayer wiring board including at least three insulating layers, first, second and third insulating layers and a semiconductor device attached to one principal surface of the first insulating layer. The first, second and third insulating layers are stacked in this order. The multilayer wiring board further includes a heat-insulating member made of a material having a lower thermal conductivity than the insulating layers. The heat-insulating member is disposed between the first and second insulating layers or next to the first insulating layer at a side opposite to the one principal surface.Type: GrantFiled: November 11, 2008Date of Patent: October 9, 2012Assignee: Panasonic CorporationInventors: Yoshihiro Tomura, Shigeru Kondou, Teppei Iwase
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Patent number: 8264079Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.Type: GrantFiled: June 26, 2008Date of Patent: September 11, 2012Assignee: Panasonic CorporationInventors: Teppei Iwase, Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa
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Patent number: 8106521Abstract: In a semiconductor device mounted structure in which device electrodes of a semiconductor device and board electrodes of a board are connected to each other via bump electrodes, respectively, and in which a sealing-bonding resin is placed between the semiconductor device and the board, a void portion is placed at a position corresponding to an edge portion of the semiconductor device in the sealing-bonding resin. Thus, stress loads generated at corner portions of the semiconductor device due to board flexures for differences in thermal expansion and thermal contraction among the individual members caused by heating and cooling during mounting of the semiconductor device, as well as for mechanical loads after the mounting process, can be absorbed by the void portion and thereby reduced, so that breakdown of the semiconductor device mounted structure is prevented.Type: GrantFiled: October 16, 2007Date of Patent: January 31, 2012Assignee: Panasonic CorporationInventors: Teppei Iwase, Yoshihiro Tomura, Kazuhiro Nobori
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Publication number: 20110279996Abstract: A multilayer wiring board is inhibited from being warped when flip-chip bonding a semiconductor device to the multilayer wiring board, thereby increasing the reliability of connecting the semiconductor assembly to a motherboard. A heat-insulating layer 10 is provided between a core board 1 and a flip-chip bonding-side insulating layer 3 in a multilayer wiring board MB1, thereby preventing thermal conduction from a heat tool, so that the amounts of thermal expansion of the core board 1 and an insulating layer 4 are minimized, resulting in reduced warpage of the multilayer wiring board MB1.Type: ApplicationFiled: November 11, 2008Publication date: November 17, 2011Inventors: Yoshihiro Tomura, Shigeru Kondou, Teppei Iwase
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Patent number: 8050049Abstract: The present invention provides a semiconductor device of a double-side mounting structure including a circuit board and a plurality of semiconductor chips arranged and joined together on the opposite surfaces of the circuit board, wherein in an area in which the semiconductor chip 31 mounted on the top surface of the circuit board 2 overlaps with the semiconductor chip 32 mounted on the bottom surface of the circuit board 2, a recess portion 21 (or a protruding portion 22) is formed in the surfaces of the circuit board 2.Type: GrantFiled: April 21, 2009Date of Patent: November 1, 2011Assignee: Panasonic CorporationInventors: Teppei Iwase, Kazuhiro Nobori, Yoshihiro Tomura, Koujiro Nakamura, Kentaro Kumazawa