Patents by Inventor Teppei MIYAJI

Teppei MIYAJI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having plural data input/output terminals configured for write test and read test operations
    Patent number: 9618575
    Abstract: Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 11, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Teppei Miyaji, Yoshinori Matsui
  • SEMICONDUCTOR DEVICE HAVING PLURAL DATA INPUT/OUTPUT TERMINALS
    Publication number: 20130265831
    Abstract: Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 10, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Teppei MIYAJI, Yoshinori MATSUI