Patents by Inventor Teppei SUDA

Teppei SUDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8466749
    Abstract: A variable gain amplifier includes a source-grounded transistor, to a gate of which an input signal is supplied; a plurality of first cascode transistors, sources of which are connected to a drain of the source-grounded transistor; a second cascode transistor, a source of which is connected to the drain of the source-grounded transistor; a first gate-grounded transistor, a source of which is connected to drains of the plurality of first cascode transistors, and to a gate of which a constant voltage is applied; and an output load connected to a drain of the first gate-grounded transistor wherein the plurality of first cascode transistors and the second cascade transistor are put into a conducting state or a non-conducting state such that a drain current of the source-grounded transistor is constant and moreover a fraction of the drain current supplied to the plurality of first cascade transistors changes.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: June 18, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jungwuk Ahn, Teppei Suda, Tomio Ueda
  • Publication number: 20120105157
    Abstract: A variable gain amplifier includes a source-grounded transistor, to a gate of which an input signal is supplied; a plurality of first cascode transistors, sources of which are connected to a drain of the source-grounded transistor; a second cascode transistor, a source of which is connected to the drain of the source-grounded transistor; a first gate-grounded transistor, a source of which is connected to drains of the plurality of first cascode transistors, and to a gate of which a constant voltage is applied; and an output load connected to a drain of the first gate-grounded transistor wherein the plurality of first cascode transistors and the second cascade transistor are put into a conducting state or a non-conducting state such that a drain current of the source-grounded transistor is constant and moreover a fraction of the drain current supplied to the plurality of first cascade transistors changes.
    Type: Application
    Filed: August 23, 2011
    Publication date: May 3, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Jungwuk AHN, Teppei SUDA, Tomio UEDA