Patents by Inventor Ter-Hoe Loh

Ter-Hoe Loh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11725942
    Abstract: A photonic integrated chip is configured as a transmitter-receiver chip. The photonic integrated chip includes a light emitter, a light detector, a multi-mode interference coupler, and a mode-filed adapter. The light emitted by the light emitter is guided to a core layer formed below the multi-mode interference coupler, and further to the mode-filed adapter for transmission of light to an optical fiber coupled with the photonic integrated chip. Similarly, light received by the mode-filed adapter from the optical fiber propagates to the core layer, and is guided by the multi-mode interference coupler into the light detector. The photonic integrated chip is utilized to realize a single-unit transmitter-receiver module for a fiber optic gyroscope circuit based on monolithic integration of photonics components via wafer fabrication on a substrate. The photonic integrated chip has a low fabrication cost, low size, and is robust.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: August 15, 2023
    Assignee: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Yee Loy Lam, Ter Hoe Loh, Kamal Kader, Long Cheng Koh
  • Publication number: 20230043322
    Abstract: A mode field adapter (MFA) is disclosed. The MFA is tapered and includes a passive core region and an active core region separated by a distance. Further, the passive core region includes first and second passive layers that are separated by another distance. The MFA is configured to receive an optical signal from a first waveguide, and alter, for transmission to a second waveguide, an optical mode of the optical signal. The optical mode is altered based on the distance between the first and second passive layers, the distance between the active and passive core regions, and the tapering of the MFA. The optical mode is altered such that an optical loss associated with the optical signal traversing from the first waveguide to the second waveguide by way of the MFA is within a tolerance limit.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 9, 2023
    Applicant: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Ter Hoe Loh, Yee Loy Lam
  • Publication number: 20220187074
    Abstract: A photonic integrated chip is configured as a transmitter-receiver chip. The photonic integrated chip includes a light emitter, a light detector, a multi-mode interference coupler, and a mode-filed adapter. The light emitted by the light emitter is guided to a core layer formed below the multi-mode interference coupler, and further to the mode-filed adapter for transmission of light to an optical fiber coupled with the photonic integrated chip. Similarly, light received by the mode-filed adapter from the optical fiber propagates to the core layer, and is guided by the multi-mode interference coupler into the light detector. The photonic integrated chip is utilized to realize a single-unit transmitter-receiver module for a fiber optic gyroscope circuit based on monolithic integration of photonics components via wafer fabrication on a substrate. The photonic integrated chip has a low fabrication cost, low size, and is robust.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 16, 2022
    Applicant: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Yee Loy Lam, Ter Hoe Loh, Kamal Kader, Long Cheng Koh
  • Publication number: 20220019021
    Abstract: A photonic integrated circuit (PIC) includes various mode field adapters (MFAs), a waveguide, and various contact pads. All the MFAs are on a same facet of the PIC. One MFA of the PIC outputs a first optical signal that is an amplified version of a second optical signal. The waveguide is divided into two waveguide arms and a bend portion to join the two waveguide arms. The waveguide extends between the MFAs such that the second optical signal propagates through the waveguide. Further, each waveguide arm is formed between the contact pads. The second optical signal propagating through the waveguide is amplified based on a current that is injected in the PIC by way of the contact pads.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 20, 2022
    Applicant: DenseLight Semiconductors Pte Ltd
    Inventors: Andy Piper, Ter Hoe Loh, Hon Yuen Aaron Sim, Long Cheng Koh, Yuen Chuen Chan, Yee Loy Lam
  • Publication number: 20130114924
    Abstract: According to embodiments of the present invention, an optical arrangement is provided. The optical arrangement includes a support substrate; at least one optical fiber arranged on the support substrate; at least one waveguide arranged on the support substrate and adjacent to the at least one optical fiber; the at least one waveguide defining a light propagation direction; and at least one grin index lens arranged asymmetrically relative to the light propagation direction such that light is coupled from the at least one optical fiber through the at least one grin index lens to the at least one waveguide.
    Type: Application
    Filed: April 26, 2011
    Publication date: May 9, 2013
    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Ter-Hoe Loh, Seng-Tiong Ho, Yingyan Huang
  • Publication number: 20110084308
    Abstract: A method for manufacturing a semiconductor arrangement is disclosed. The method comprises forming at least one trench in a dielectric layer, thereby exposing a portion of a semiconductor substrate, forming a silicon-germanium buffer layer at least on the bottom of the at least one trench, forming a germanium seed layer on the silicon-germanium buffer layer and forming a germanium layer on the germanium seed layer. A semiconductor arrangement is also disclosed. The semiconductor arrangement comprises a semiconductor substrate, a dielectric layer disposed above the semiconductor substrate, at least one trench in the dielectric layer exposing a portion of the semiconductor substrate, a silicon-germanium buffer layer disposed above at least the bottom of the at least one trench, a germanium seed layer disposed above the silicon-germanium buffer layer and a germanium layer disposed above the germanium seed layer.
    Type: Application
    Filed: August 8, 2007
    Publication date: April 14, 2011
    Inventors: Ter-Hoe Loh, Hoai-Son Nguyen