Patents by Inventor Terani N. Vijaykumar

Terani N. Vijaykumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220374235
    Abstract: A method of verifying authenticity of a speculative load instruction is disclosed which includes receiving a new speculative source-destination pair (PAIR), wherein the source represents a speculative load instruction and the destination represents an associated destination virtual memory location holding data to be loaded onto a register with execution of the source, checking the PAIR against one or more memory tables associated with non-speculative source-destination pairs, if the PAIR exists in the one or more memory tables, then executing the instruction associated with the source of the PAIR, if the PAIR does not exist, then i) waiting until the speculation of the source instruction has cleared as being non-speculative, ii) updating the one or more memory tables, and iii) executing the instruction associated with the source, and if the speculation of the source instruction of the PAIR does not clear as non-speculative, then the source is nullified.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 24, 2022
    Applicant: Purdue Research Foundation
    Inventors: Mithuna Shamabhat Thottethodi, Terani N Vijaykumar
  • Patent number: 11190454
    Abstract: A receiver-directed congestion control system which provides receiver-directed apportioning by adding a bandwidth share indicator value to the acknowledgement messages sent by the receiver to the senders. In certain embodiments, bandwidth share indicator value comprises the number of senders seen by the receiver. In other embodiments, the bandwidth share indicator value may comprise a percentage bandwidth share allocated to the sender computer to allow for varying priorities between senders. In the acknowledgement message, each sender may also include the incast degree, which is programmed in the application, to the receiver. This strategy enables the receiver to send back the sender count to all the senders as soon the first sender's packets arrive, even before the rest of the senders' packets arrive. Thus, the sender count and the incast degree look-ahead enable the receiver-directed system to achieve accurate and faster convergence of sending rates, without any repeated adjustments.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: November 30, 2021
    Assignee: Purdue Research Foundation
    Inventors: Mithuna Shamabhat Thottethodi, Terani N. Vijaykumar, Balajee Vamanan, Jiachen Xue
  • Patent number: 11134031
    Abstract: A remote indirect memory access system and method for networked computer servers. The system comprises a network interface card having a network interface memory and a system memory operatively connected to the network interface card. The system memory has a plurality of electronic memory queues, wherein each of the memory queues corresponds to one of a plurality of receive processes in the computer server, with each of the memory queues having a corresponding head pointer and tail pointer. Each of the memory queues is assigned to receive electronic messages from a plurality of sender computers. The NIC comprises a tail pointer table, with the tail pointer table comprising initial memory location data of the tail pointers for the memory queues. The memory location data referenced by corresponding queue identifiers.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 28, 2021
    Assignee: Purdue Research Foundation
    Inventors: Mithuna Shamabhat Thottethodi, Terani N Vijaykumar, Jiachen Xue
  • Publication number: 20200296059
    Abstract: A remote indirect memory access system and method for networked computer servers. The system comprises a network interface card having a network interface memory and a system memory operatively connected to the network interface card. The system memory has a plurality of electronic memory queues, wherein each of the memory queues corresponds to one of a plurality of receive processes in the computer server, with each of the memory queues having a corresponding head pointer and tail pointer. Each of the memory queues is assigned to receive electronic messages from a plurality of sender computers. The NIC comprises a tail pointer table, with the tail pointer table comprising initial memory location data of the tail pointers for the memory queues. The memory location data referenced by corresponding queue identifiers.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 17, 2020
    Applicant: Purdue Research Foundation
    Inventors: Mithuna Shamabhat Thottethodi, Terani N Vijaykumar, Jiachen Xue
  • Publication number: 20190140962
    Abstract: A receiver-directed congestion control system which provides receiver-directed apportioning by adding a bandwidth share indicator value to the acknowledgement messages sent by the receiver to the senders. In certain embodiments, bandwidth share indicator value comprises the number of senders seen by the receiver. In other embodiments, the bandwidth share indicator value may comprise a percentage bandwidth share allocated to the sender computer to allow for varying priorities between senders. In the acknowledgement message, each sender may also include the incast degree, which is programmed in the application, to the receiver. This strategy enables the receiver to send back the sender count to all the senders as soon the first sender's packets arrive, even before the rest of the senders' packets arrive. Thus, the sender count and the incast degree look-ahead enable the receiver-directed system to achieve accurate and faster convergence of sending rates, without any repeated adjustments.
    Type: Application
    Filed: March 23, 2017
    Publication date: May 9, 2019
    Applicant: Purdue Research Foundation
    Inventors: Mithuna Shamabhat THOTTETHODI, Terani N. VIJAYKUMAR, Balajee VAMANAN, Jiachen XUE
  • Publication number: 20040168078
    Abstract: An apparatus, system, and method for protecting a computing device from attacks while the computing device is in operation is provided. In one embodiment, the apparatus includes an input/output unit, a control unit, an execute unit, and first and second memory areas. The first memory area is accessible by a user of the computing device. The second memory area is not accessible by any users. The second memory area is configured to store return addresses and stack pointers.
    Type: Application
    Filed: December 2, 2003
    Publication date: August 26, 2004
    Inventors: Carla E. Brodley, Terani N. Vijaykumar, Hilmi Ozdoganoglu, Benjamin A. Kuperman
  • Patent number: 5781752
    Abstract: A predictor circuit permits advanced execution of instructions depending for their data on previous instructions by predicting such dependencies based on previous mis-speculations detected at the final stages of processing. Synchronization of dependent instructions is provided by a table creating entries for each instance of potential dependency. Table entries are created and deleted dynamically to limit total memory requirements.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: July 14, 1998
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Andreas I. Moshovos, Scott E. Breach, Terani N. Vijaykumar, Gurindar S. Sohi