Abstract: A regulated cascode current source has a current source circuit. A level shifter circuit is coupled to the current source circuit. The level shifter circuit has a circuit for independently controlling a voltage on a cascode node.

Abstract: A Digital to Analog (D/A) converter has a plurality of stages. Each of the plurality of stages has a first resistive element. A second resistive element is coupled to the first resistive element and has approximately twice a resistive value of the first resistive element. A capacitor is coupled to the second resistive element. A switching circuit is coupled to the capacitor. A summing integrator is coupled to each of the plurality of stages.

Abstract: A Digital to Analog (D/A) converter has a plurality of stages. Each of the plurality of stages has a first resistive element. A second resistive element is coupled to the first resistive element and has approximately twice a resistive value of the first resistive element. A capacitor is coupled to the second resistive element. A switching circuit is coupled to the capacitor. A summing integrator is coupled to each of the plurality of stages.

Abstract: A regulated cascode current source has a current source circuit. A level shifter circuit is coupled to the current source circuit. The level shifter circuit has a circuit for independently controlling a voltage on a cascode node.

Abstract: A switched-capacitor sample/hold circuit and method having reduced slew-rate and settling time requirements provides for lower-cost and/or lower-power implementation of sample/hold circuits and/or reduced error due to amplifier characteristics. The switched-capacitor sample/hold circuit incorporates a pair of capacitors that are alternatively and mutually-exclusively switched between an input sample position and an amplifier hold position, providing a dual sampled amplifier output signal that has reduced transitions at each sample interval. An alternative embodiment of the sample/hold circuit incorporates a fully-differential amplifier having a differential input and a differential output. Four capacitors are employed forming two of the dual sampled switched-capacitor circuits, one in each negative feedback path (inverted output to non-inverting input, non-inverted output to inverting input) of the amplifier.

Abstract: A switched-capacitor sample/hold circuit and method having reduced slew-rate and settling time requirements provides for lower-cost and/or lower-power implementation of sample/hold circuits and/or reduced error due to amplifier characteristics. The switched-capacitor sample/hold circuit incorporates a pair of capacitors that are alternatively and mutually-exclusively switched between an input sample position and an amplifier hold position, providing a dual sampled amplifier output signal that has reduced transitions at each sample interval. An alternative embodiment of the sample/hold circuit incorporates a fully-differential amplifier having a differential input and a differential output. Four capacitors are employed forming two of the dual sampled switched-capacitor circuits, one in each negative feedback path (inverted output to non-inverting input, non-inverted output to inverting input) of the amplifier.